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参数资料
| 型号： | MK2059-01SILFTR |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/11页 |
| 文件大小： | 0K |
| 描述： | IC VCXO CLK JITTER ATTEN 20-SOIC |
| 标准包装： | 1,000 |
| 类型： | 时钟频率变换器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 25.92MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 带卷 (TR) |
MK2059-01
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
VCXO AND SYNTHESIZER
IDT VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
3
MK2059-01
REV H 051310
Functional Description
The MK2059-01 is a clock generator IC that generates an
output clock directly from an internal VCXO circuit which
works in conjunction with an external quartz crystal. The
VCXO is controlled by an internal PLL (Phase Locked Loop)
circuit, enabling the device to perform clock regeneration
from an input reference clock. The MK2059-01 is configured
to provide a MHz communications reference clock output
from an 8kHz input clock. There are 12 selectable output
frequencies. Please refer to the Output Clock Selection
Table on Page 2.
Most typical PLL clock devices use an internal VCO (Voltage
Controlled Oscillator) for output clock generation. By using
a VCXO with an external crystal, the MK2059-01 is able to
generate a low jitter, low phase-noise output clock within a
low bandwidth PLL. This serves to provide input clock jitter
attenuation and enables stable operation with a low
frequency reference clock.
The VCXO circuit requires an external pullable crystal for
operation. External loop filter components enable a PLL
configuration with low loop bandwidth.
Application Information
Output Frequency Configuration
The MK2059-01 is configured to generate a set of output
frequencies from an 8kHz input clock. Please refer to the
Output Clock Selection Table on Page 2. Input bits SEL2:0
are set according to this table, as is the external crystal
frequency. Please refer to the Quartz Crystal section on this
page regarding external crystal requirements.
Input Mux
The Input Mux serves to select between two alternate input
reference clocks. Upon reselection of the input clock, clock
glitches on the output clock will not be generated due to the
“fly-wheel” effect of the VCXO (the quartz crystal is a high-Q
tuned circuit). When the input clocks are not phase aligned,
the phase of the output clock will change to reflect the phase
of newly selected input at a controlled phase slope (rate of
phase change) as influenced by the PLL loop
characteristics.
Quartz Crystal
It is important that the correct type of quartz crystal is used
with the MK2059-01. Failure to do so may result in reduced
frequency pullability range, inability of the loop to lock, or
excessive output phase jitter.
The MK2059-01 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input. The
VCXO consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best performance
and reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the PCB Layout Recommendations
section must be followed.
The frequency of oscillation of a quartz crystal is determined
by its cut and by the external load capacitance. The
MK2059-01 incorporates variable load capacitors on-chip
which “pull”, or change, the frequency of the crystal. The
crystals specified for use with the MK2059-01 are designed
to have zero frequency error when the total of on-chip +
stray capacitance is 14pF. To achieve this, the layout should
use short traces between the MK2059-01 and the crystal.
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish operating
stability. The MK2059-01 uses external loop filter
components for the following reasons:
1) Larger loop filter capacitor values can be used, allowing
a lower loop bandwidth. This enables the use of lower input
clock reference frequencies and also input clock jitter
attenuation capabilities. Larger loop filter capacitors also
allow higher loop damping factors when less passband
peaking is desired.
2) The loop filter values can be user selected to optimize
loop response characteristics for a given application.
Referencing the External Component Schematic on this
page, the external loop filter is made up of components RS,
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK2059-01SITR | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2069-01 | 制造商:ICS 制造商全称:ICS 功能描述:VCXO-Based Line Card Clock Synchronizer |
| MK2069-01GI | 功能描述:IC VCXO CLK SYNCHRONIZER 56TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| MK2069-01GILF | 功能描述:时钟合成器/抖动清除器 VCXO-BASED LINE CARD CLOCK SYNCHRONIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MK2069-01GILFTR | 功能描述:时钟发生器及支持产品 VCXO-BASED LINE CARD CLOCK SYNCHRONIZER RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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