参数资料
型号: MK2771-05S
元件分类: 时钟产生/分配
英文描述: 50 MHz, OTHER CLOCK GENERATOR, PDSO20
封装: SOIC-20
文件页数: 2/4页
文件大小: 103K
代理商: MK2771-05S
MK2771-05
VCXO and Set-Top Clock Source
MDS2771-05B
2
Revision 2038
Printed 11/8/99
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Pin Descriptions
Key: I = Input, TI = Tri-level input, VI = VCXO input, O = output, P = power supply connection
Pin Assignment
Number
Name
Type
Description
1
PCS0
I
Processor Clock Select 0. Determines PCLK frequency, as per table above.
2
X2
O
Crystal connection. Connect to a pullable 14.31818 MHz crystal.
3
X1
I
Crystal connection. Connect to a pullable 14.31818 MHz crystal.
4
AVDD
P
Connect to +5V, and other VDDs.
5
VIN
VI
Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.
6
VDD
P
Connect to +5V.
7
GND
P
Connect to ground.
8
PCLK
O
Processor Clock Output determined by PCS1 and PCS0, as per table above.
9
ACLK
O
Audio Clock Output determined by ACS, as per table above.
10
VDD
P
Connect to +5V.
11
GND
P
Connect to ground.
12
16.0M
O
16.0000 MHz clock output.
13
DC
-
Do Not Connect.
14
GND
P
Connect to ground.
15
VDD
P
Connect to +5V.
16
14.3M
O
14.31818 MHz clock output.
17
GND
P
Connect to ground.
18
27M
O
27.00 MHz clock output.
19
ACS
T I
Audio Clock Select. Determines ACLK frequency, as per table above.
20
PCS1
T I
Processor Clock Select 1. Determines PCLK frequency, as per table above.
1
16
2
3
4
15
14
13
AVDD
GND
X2
VDD
GND
5
6
7
8
12
11
10
9
VDD
ACS
X1
PCS0
27M
PCS1
14.3M
DC
GND
ACLK
PCLK
18
17
19
20
VIN
VDD
16.0M
GND
PCS1 PCS0 PCLK (MHz)
00
32
0
1
39.5
1
0
Tri-state PCLK
11
50
Processor Clock
ACS
ACLK (MHz)
0
22.5792
1
24.576
Audio Clock
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