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参数资料
| 型号： | MK2772-01SLFTR |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 27 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | LEAD FREE, SOIC-20 |
| 文件页数： | 3/4页 |
| 文件大小： | 483K |
| 代理商： | MK2772-01SLFTR |
MK2772-01
VCXO and Set-Top Clock Source
MDS 2772-01 D
3
Revision 102704
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Parameter
Conditions
Minimum
Typical Maximum Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5.0V unless noted)
Operating Voltage, VDD
4.75
5.25
V
Input High Voltage, VIH, X1 pin only
3.5
2.5
V
Input Low Voltage, VIL, X1 pin only
2.5
1.5
V
Input High Voltage, VIH
ACS1, ACS0
VDD-0.5
V
Input High Voltage, VIH
INMUXSEL
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load, note 2
45
mA
Pull-up Resistor value
pin 11 only
250k
Input Capacitance
7
pF
Frequency synthesis error
All clocks as shown
0
1
ppm
VIN, VCXO control voltage
0
3
V
AC CHARACTERISTICS (VDD = 5.0V unless noted)
Input Crystal Frequency
13.50000
MHz
Input Crystal Accuracy
±30
ppm
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At 1.4V
40
60
%
Maximum Absolute Jitter, short term
300
ps
27 MHz output pullability, note 3
0V < VIN < 3V'
±100
ppm
Electrical Specifications
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the
device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect
device reliability.
2. With ACLK at 12.288 MHz.
3. With a recommended crystal.
External Components/Crystal Selection
The MK2772-01 requires a minimum number of external components for proper operation. Decoupling capacitors
of 0.1F should be connected between VDD (pin 15) and GND (14), and between VDD (4) and GND (7), as close to
the MK2772-01 as possible. A series termination resistor of 33
may be used for each clock output. The input
crystal must be connected as close to the chip as possible.
For the VCXO to operate correctly, a crystal properly specified and matched to the MK2772-01 must be used. For
more information, including a list of recommended crystals, refer to application note MAN05.
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