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参数资料
| 型号： | MK3727S |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 27 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 0.150 INCH, SOIC-8 |
| 文件页数： | 2/7页 |
| 文件大小： | 136K |
| 代理商： | MK3727S |
LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO
MDS 3727 L
2
Revision 091205
In te gr ated Circuit Systems
525 Race Stree t , Sa n Jose, CA 9 512 6
tel (4 08) 2 97-12 01
www.icst.com
MK3727
Pin Assignment
Pin Descriptions
X1
VDD
VI N
GN D
GND
NC
CL K
X2
1
2
3
4
8
7
6
5
MK3727 C
MK3727 D
8- Pi n ( 150 mi l ) SOI C
X1
VD D
VI N
GND
GN D
VDD
CL K
X2
1
2
3
4
8
7
6
5
M K 372 7S
8- Pi n ( 150 mi l ) SO I C
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
XI
Input
Crystal connection — Connect to the external pullable crystal.
2
VDD
Power
Connect to +3.3 V (0.01uf decoupling capacitor recommended)
3
VIN
Input
Voltage input to VCXO — 0 to 3.3 V analog input which controls the
oscillation frequency of the VCXO.
4
GND
Power
Connect to ground
5
CLK
Output
Clock output
6 (3727C/D)
NC
—
No internal connection (may connect to ground or VDD)
6 (3727S)
VDD
Power
Connect to VDD
7
GND
Power
Connect to ground
8
X2
Input
Crystal connection — Connect to the external pullable crystal.
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| MK3727SLF | 制造商:Integrated Device Technology Inc 功能描述:IDT MK3727SLF PHASED LOCKED LOOP (PLL) - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:IDT MK3727SLF Phased Locked Loop (PLL) |
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