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参数资料
| 型号： | MK3732-15G |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 108 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.173 INCH, TSSOP-16 |
| 文件页数： | 2/4页 |
| 文件大小： | 61K |
| 代理商： | MK3732-15G |
MK3732-15
Low Phase Noise VCXO+Multiplier
PRELIMINARY INFORMATION
MDS 3732-15 A
2
Revision 082800
Printed 11/16/00
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408) 295-9800tel www.icst.com
Pin Descriptions
Key: I = Input with internal pull-up resistor; TI = tri-level input; O = output; P = power supply connection;
VI = analog voltage input; XI, XO = crystal pins.
Pin Assignment
Number
Name
Type
Description
1
X1
XI
Crystal connection. Connect to a pullable crystal of 10-18 MHz.
2, 3, 11
VDD
P
VDD. Connect to +3.3V.
4
VIN
VI
Voltage Input to VCXO. Zero to 3.3 V signal which controls the frequency of the VCXO.
5, 6, 13
GND
P
Connect to ground.
7
S2
I
Select input #2. Selects CLK output per table above.
8
OE
I
Output Enable. Tri-states outputs when low.
9
S0
TI
Select input #0. Selects CLK output per table above.
10
REFEN
I
Reference Enable (active low). When pin is connected to ground, the REFCLK is running.
12
CLK
O
VCXO Clock Output per table above.
14
REFCLK
O
Buffered crystal VCXO clock
15
S1
I
Select input #1. Selects CLK output per table above.
16
X2
XO
Crystal connection. Connect to a pullable crystal of 10-18 MHz.
MK3732-15
External Components
The MK3732-15 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01F should be connected between VDD and GND on pins 3 and 5, and VDD and GND
on pins 11 and 13, as close to the MK3732-15 as possible. A series termination resistor of 33
may be used
for each clock output. The input crystal must be connected as close to the chip as possible. The input crystal
should be a fundamental mode, parallel resonant, pullable, AT cut. A crystal with 14 pF load capacitance is
recommended. Consult ICS/MicroClock for recommended suppliers. IMPORTANT - consult the
application note MAN05 for layout guidelines.
16
15
14
13
16 pin (173 mil) TSSOP
12
11
10
9
1
2
3
4
5
6
7
8
VDD
GND
X2
X1
VIN
OE
GND
S2
GND
CLK
REFEN
S0
VDD
S1
REFCLK
S2
S1
S0
CLK
0
REF/2
0
M
x0.666
0
1
x2.6666
0
1
0
x4
0
1
M
x1.5
0
1
x1.3333
1
0
Test
1
0
M
x4
1
0
1
x2
1
0
x3
1
M
x5
1
x6
0 = connect directly to GND, M = leave unconnected
(floating), 1 = connect directly to VDD.
Clock Select Table
For Analog Devices’
ADSL chipset, use a
17.664 MHz crystal,
and the 101 setting
for a 35.328 MHz
output clock. Pin 10
should be grounded
to get the 17.664 MHz
clock output on pin 14.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MK3732-17 | 制造商:ICS 制造商全称:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-17S | 功能描述:时钟合成器/抖动清除器 ADSL VCXO CLOCK SOURCE RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MK3732-17SI | 制造商:ICS 制造商全称:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-17SITR | 制造商:ICS 制造商全称:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-17STR | 功能描述:时钟合成器/抖动清除器 ADSL VCXO CLOCK SOURCE RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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