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参数资料
| 型号： | MK3732-15G |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 108 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.173 INCH, TSSOP-16 |
| 文件页数： | 3/4页 |
| 文件大小： | 61K |
| 代理商： | MK3732-15G |
MK3732-15
Low Phase Noise VCXO+Multiplier
PRELIMINARY INFORMATION
MDS 3732-15 A
3
Revision 082800
Printed 11/16/00
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408) 295-9800tel www.icst.com
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Core Operating Voltage, VDD
3.15
3.30
3.45
V
Input High Voltage, VIH, X1 pin only
3.5
2.5
V
Input Low Voltage, VIL, X1 pin only
2.5
1.5
V
Input High Voltage, VIH, binary input
OE
2
V
Input Low Voltage, VIL, binary input
OE
0.8
V
Input High Voltage, VIH, trinary inputs
S1, S0
VDD-0.5
V
Input Low Voltage, VIL, trinary inputs
S1, S0
0.5
V
Output High Voltage, VOH
IOH=-12mA
2.4
V
Output Low Voltage, VOL
IOL=12mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load
9
mA
Short Circuit Current
Each output
±50
mA
Input Capacitance
S1, S0, OE
5
pF
Frequency synthesis error
All clocks
0
ppm
VIN, VCXO control voltage
0
3.3
V
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Crystal Frequency
10
18
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At VDD/2
40
60
%
Maximum Absolute Jitter, short term
±150
ps
Phase Noise, relative to carrier, note 3
10 kHz offset
-115
dBc/Hz
Output pullability, note 2
0V
≤ VIN ≤ 3.3V
±100
ppm
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With an ICS/MicroClock approved pullable crystal.
3. To achieve this level of phase noise (lowest), REFCLK must be turned off by connecting REFEN to VDD.
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相关代理商/技术参数 |
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| MK3732-17 | 制造商:ICS 制造商全称:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-17S | 功能描述:时钟合成器/抖动清除器 ADSL VCXO CLOCK SOURCE RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| MK3732-17SI | 制造商:ICS 制造商全称:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-17SITR | 制造商:ICS 制造商全称:ICS 功能描述:ADSL VCXO CLOCK SOURCE |
| MK3732-17STR | 功能描述:时钟合成器/抖动清除器 ADSL VCXO CLOCK SOURCE RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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