参数资料
型号: MK41T56N00
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP8
封装: 0.40 MM LEAD FRAME, SKINNY, PLASTIC, DIP-8
文件页数: 13/16页
文件大小: 105K
代理商: MK41T56N00
MK41T56, MKI41T56
6/16
Table 9. Power Down/Up Mode AC Characteristics
(TA = 0 to 70 °C or –40 to 85°C)
Symbol
Parameter
Min
Max
Unit
tPD
SCL and SDA at VIH before Power Down
0ns
tFB
VPFD (min) to VSO VCC Fall Time
300
s
tRB
VSO to VPFD (min) VCC Rise Time
100
s
tREC
SCL and SDA at VIH after Power Up
200
s
Figure 6. Power Down/Up Mode AC Waveforms
AI00595
VCC
tFB
tREC
tPD
tRB
VPFD
VSO
DATA RETENTION TIME
SDA
SCL
IBAT
2-WIRE BUS CHARACTERISTICS
This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock sig-
nals (SCL). Both the SDA and the SCL lines must
be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line while the clock line is
High will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the High period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
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