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参数资料
| 型号： | MK74CB177RLF |
| 元件分类： | 时钟及定时 |
| 英文描述： | CB SERIES, LOW SKEW CLOCK DRIVER, 7 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 0.150 INCH, SSOP-28 |
| 文件页数： | 2/4页 |
| 文件大小： | 48K |
| 代理商： | MK74CB177RLF |
MK74CB177
OPTi Buffalo Clock Driver
MDS74CB177B
2
Revision 3038
Printed 3/3/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Number
Name
Type
Description
1
INA
I
Clock input for eight A outputs.
2, 3, 4
QA0, QA1, QA2
O
Clock A outputs.
5, 6
VDDA
P
Power supply for eight A buffers. Connect to +3.3V or +5V. Clock amplitude will match.
7, 8
QA3, QA4
O
Clock A outputs.
9, 10
GNDA
P
Connect to ground.
11, 12, 13 QA5, QA6, QA7
O
Clock A outputs. QA7 does not stop when PDA06 is low. Always runs.
14
PDA06
I
Power Down (active low). Stops QA0-QA6 clock outputs low.
15
INC
I
Clock input for one C output. Typically connect the early CPU clock to this pin.
16
QC0
O
Clock C output. Typically connect to core logic for early clock.
17, 18
QB6, QB5
O
Clock B outputs.
19, 20
GNDBC
P
Connect to ground.
21, 22
QB4, QB3
O
Clock B outputs.
23, 24
VDDBC
P
Power supply for B and C buffers. Connect to +3.3V or +5V. Clock amplitude will match.
25, 26, 27 QB2, QB1, QB0
O
Clock B outputs.
28
INB
I
Clock input for seven B outputs.
Pin Descriptions
Type: I = Input, O = output, P = power supply connection
Important: PDA06 input signal must be less than or equal to VDDA. So a 5V signal on PDA06
combined with VDDA=3.3V is not allowed.
Pin Assignment
1
8
9
2
3
4
5
6
7
10
11
12
13
14
QA0
QA1
QA2
QA3
QA4
QA5
QA7
QA6
INA
GNDA
PDA06
VDDA
QB0
QB1
QB2
QB3
QB4
QB5
QC0
QB6
INB
GNDB
INC
VDDB
16
15
17
18
19
20
21
22
23
24
25
28
27
26
Suggested Layout
V
G
V
For simplicity, terminating resistors (if needed) are not
shown for the outputs, but should be placed as close to the
device as possible. It is most critical to have the 0.1F
decoupling capacitors closest.
V = connect to VDD
= connect to GND
G
0.1F
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