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参数资料
| 型号： | MK74CB177RLF |
| 元件分类： | 时钟及定时 |
| 英文描述： | CB SERIES, LOW SKEW CLOCK DRIVER, 7 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 0.150 INCH, SSOP-28 |
| 文件页数： | 3/4页 |
| 文件大小： | 48K |
| 代理商： | MK74CB177RLF |
MK74CB177
OPTi Buffalo Clock Driver
MDS74CB177B
3
Revision 3038
Printed 3/3/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
0.5
VDD+0.5
V
Clock Outputs
Referenced to GND
0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 20 seconds
260
°C
Storage Temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5V unless noted)
Operating Voltage, VDD
3.0
5.5
V
Input High Voltage, VIH (INA, INB, INC pins)
VDD-1
VDD/2
V
Input Low Voltage, VIL (INA, INB, INC pins)
VDD/2
1
V
Input High Voltage, VIH (PDA06 pin)
2.0
V
Input Low Voltage, VIL (PDA06 pin)
0.8
V
Output High Voltage, 3.3V and 5V
IOH=-8mA
VDD-0.4
V
Output High Voltage, 3.3V and 5V
IOH=-12mA
2.4
V
Output Low Voltage, 3.3V and 5V
IOL=12mA
0.8
V
Operating Supply Current, IDD, at 66.6MHz
No Load
20
mA
Short Circuit Current
Each output
±70
mA
Short Circuit Current at 3.3V
Each output
±35
mA
Input Capacitance
7
pF
AC CHARACTERISTICS (VDD = 5V unless noted)
Input Clock Frequency
67
MHz
Propagation Delay with load=10pF
2
3.5
5
ns
Propagation Delay with load=10pF
At VDD=3.3V
2.5
4.5
6.5
ns
Output Clock Rise Time, 3.3V and 5V
0.8 to 2.0V
1.5
ns
Output Clock Fall Time, 3.3V and 5V
2.0 to 0.8V
1.5
ns
Output Clock Rising Edge Skew, 3.3V and 5V
At VDD/2. Note 2
50
250
ps
Output Clock A to B to C Skew, 3.3V and 5V
At VDD/2. Note 3
100
500
ps
Output Enable Time, PDA06 high to output on
5
20
ns
Output Disable Time, PDA06 low to tri-state
65
100
ns
Maximum load per output pin
At 66.66 MHz
25
pF
Maximum load per side of 8 outputs
Note 4
120
pF
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Between any two A outputs, or any two B outputs, with equal loading.
3. Between any clock A or clock B or clock C outputs with inputs connected. With VDDA=VDDBC and equal loading. Combined
with the 250ps uncertainty of MicroClock’s Clock Synthesizers, this adds to a 750ps total. The new PCI specifications allow a 2ns
difference between PCI and CPU clocks.
4. This is the load per sum of all A outputs, or all B+C outputs, at 66.66MHz. The formula for per side load is CL (F) =
8 x 10-3
f (in Hz)
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