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参数资料
| 型号： | ML53812-2 |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP176 |
| 封装： | LQFP-176 |
| 文件页数： | 26/64页 |
| 文件大小： | 668K |
| 代理商： | ML53812-2 |
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s ML53812-2 s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
28
Oki Semiconductor
Configuration Register Byte 12, AR = 000ch
DR_0
C
Definition
0
96
Direct Parallel Access Enable
1
97
Microprocessor Watchdog Enable
2
98
APLL Clock Watchdog Enable
3
99
Reserved
4
100
Message Channel Registered TXD Enable
5
101
Message Channel Output Disable
6
102
Reserved
7
103
Reserved
Direct Parallel Access Enable (C_ [96]) (Read/Write)
0
→
Direct Parallel Access disabled (Default)
1
→
Direct Parallel Access enabled
Microprocessor Watchdog Enable (C_ [97]) (Read/Write)
When enabled, the ML53812-2 enters into reset after the Analog PLL clocks for 256mS (± 50%).
Each time C_[97] is cleared (0) and then set (1), the microprocessor watchdog count is reset.
0
→
Microprocessor Watchdog disabled (Default)
1
→
Microprocessor Watchdog enabled
APLL Clock Watchdog Enable (C_ [98]) (Read/Write)
When enabled, C_[98] will read back as being set (1) until the Analog PLL clocks for 125 S (± 50%), then will read back as being cleared (0). Each
time C_[98] is cleared (0) and then set (1), the clock watchdog count is reset.
0
→
APLL Clock Watchdog disabled (Default)
1
→
APLL Clock Watchdog enabled
Message Channel Registered TXD Enable (C_ [100]) (Read/Write)
0
→
MC_TXD passed though to CT_MC (Default)
1
→
MC_TXD registered to CT_MC on rising edge of MC_CLK
Message Channel Output Disable with Loop-back (C_ [101]) (Read/Write)
When CT_MC output is disabled, the local message channel circuitry can be tested without disturbing the CT Bus.
0
→
CT_MC Output enabled (Default)
1
→
CT_MC Output Tri-stated, MC_TXD looped back to MC_RXD
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