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参数资料
| 型号： | ML54053 |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 存储控制器/管理单元 |
| 英文描述： | IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PQFP120 |
| 封装： | 14 X 14 MM, 0.40 MM PITCH, PLASTIC, TQFP-120 |
| 文件页数： | 13/26页 |
| 文件大小： | 235K |
| 代理商： | ML54053 |
Semiconductor
ML54053
16/22
6.6 Number of Installed Memory Chips and CHS Structure
NAND flash memory is erased in block units. Since block erasing is also performed during a 1-
page (sector) write, efficiency is increased during write operations by serially addressing sectors
within the same block.
The CHS structure and number of installed memory chips when using 64, 128, 256 and 512 Mbit
memory are listed below (where C is the default value). The C value of the CHS address can be
set by the change physical cylinder command (a vendor-unique command).
64 Mbit Memory
Capacity
No. of Chips
CHS
H
LBA Max. (Hex)
CS
8
16
32
1
2
4
1000
1
2
16
32
16000
32000
64000
(3E80)
(7D00)
(FA00)
128 Mbit Memory
Capacity
No. of Chips
CHS
H
LBA Max. (Hex)
CS
16
32
64
1
2
4
1000
1
2
32
64
32000
64000
128000
(7D00)
(FA00)
(1F400)
256 Mbit Memory
Capacity
No. of Chips
CHS
H
LBA Max. (Hex)
CS
32
64
128
1
2
4
1000
2
4
32
64
64000
128000
256000
(FA00)
(1F400)
(3E800)
512 Mbit Memory
Capacity
No. of Chips
CHS
H
LBA Max. (Hex)
CS
64
128
256
1
2
4
1000
4
8
32
64
128000
256000
512000
(1F400)
(3E800)
(7D000)
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