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参数资料
| 型号： | ML63295A-XXXWA |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC212 |
| 封装： | 8.25 X 8.20 MM, 0.35 MM HEIGHT, DIE-212 |
| 文件页数： | 10/39页 |
| 文件大小： | 253K |
| 代理商： | ML63295A-XXXWA |
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FEDL63295A-02
1Semiconductor
ML63295A
17/38
Table 2 shows the secondary functions of each pin of the ML63295A.
Table 2 Pin Descriptions (Secondary Functions)
Function
Symbol
Pin No.
Pad No.
Type
Description
PB.0/INT0
196
12
PB.1/INT0
195
11
PB.2/INT0
194
10
PB.3/INT0
193
9
I
External 0 interrupt input pins
The change of input signal level causes an
interrupt to occur.
The Port B Interrupt Enable register (PBIE)
enables or disables an interrupt for each bit.
PC.0/INT1
192
8
PC.1/INT1
191
7
PC.2/INT1
190
6
PC.3/INT1
189
5
I
External 1 interrupt input pins
The change of input signal level causes an
interrupt to occur.
The Port C Interrupt Enable register (PCIE)
enables or disables an interrupt for each bit.
PE.3/INT2
185
1
I
External 2 interrupt input pin
The change of input signal level causes an
interrupt to occur.
P8.3/INT4
205
21
I
External 4 interrupt input pin
The change of input signal level causes an
interrupt to occur.
P0.0/INT5
5
56
P0.1/INT5
4
55
P0.2/INT5
3
54
P0.3/INT5
237
53
P1.0/INT5
236
52
P1.1/INT5
235
51
P1.2/INT5
234
50
External
Interrupt
P1.3/INT5
233
49
I
External 5 interrupt input pins
The change of input signal level causes an
interrupt to occur.
The Port 0 Interrupt Enable register (P0IE)
and Port 1 Interrupt Enable register (P1IE)
enable or disable an interrupt for each bit.
PB.2/T2CK
194
10
I
External clock input pin for timer 2
Timer
PB.3/T3CK
193
9
I
External clock input pin for timer 3
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