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参数资料
| 型号： | ML67Q5003LA |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封装： | 11 X 11 MM, 0.80 MM PITCH, PLASTIC, LFBGA-144 |
| 文件页数： | 9/25页 |
| 文件大小： | 233K |
| 代理商： | ML67Q5003LA |
FEDL675001-01
OKI Semiconductor
ML675001/67Q5002/67Q5003
16/24
GPIO
42-bits parallel port (four 8-bit ports and one 10-bit port)
.
PIOA[7:0]
Combination port
UART
PIOB[7:0]
Combination port
DMAC, UART(uPLAT-7B),
PIOC[7:0]
Combination port
PWM, XA[23:19], XWR
PIOD[7:0]
Combination port
DRAM contorol signal etc.
PIOE[9:0]
Combination port
SSIO, I2C, External interrupt signal
(1) Input/output selectable at bit level.
(2) Each bit can be used as an interrupt source.
(3) Interrupt mask and interrupt polarity can be set for all bits.
(4) The ports are configured as input, immediately after reset.
(5) Primary/secondary function of each port can be set independently.
AD Converter
Successive approximation type AD converter.
(1)
10 bits
× 4 channels
(2)
Sample hold function
(3)
Scan mode and select mode are supported
(4)
Interrupt is generated after completion of conversion.
(5)
Conversion time: 5 s minimum.
DMAC
Two channels of direct memory access controller which transfers data between memory and memory, between
I/O and memory and between I/O and I/O.
(1)
Number of channels: 2 channels
(2)
Channel priority level: Fixed mode
Channel priority level is always fixed (channel 0 > 1).
Roundrobin
Priority level of the channel requested for transfer is kept lowest.
(3)
Maximum number of transfers: 65,536 times (64K times)
(4)
Data transfer size: Byte (8 bits), half-word (16 bits), word (32 bits)
(5)
Bus request system:
Cycle steal mode
Bus request signal is asserted for each DMA transfer cycle.
Burst mode
Bus request signal is asserted until all transfers of transfer cycles are complete.
(6)
DMA transfer request: Software request
By setting the software transfer request bit inside DMAC, the CPU starts DMA
transfer.
External request
DMA transfer is started by external request allocated to each channel.
(7)
Interrupt request: Interrupt request is generated to CPU after
the end of DMA transfers for the set
number of transfer cycles or after occurrence of error.
Interrupt request signal is output separately for each channel.
Interrupt request signal output can be masked for each channel.
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