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参数资料
| 型号： | ML69Q6203LA |
| 厂商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PBGA272 |
| 封装： | 15 X 15 MM, 0.65 PITCH, PLASTIC, LFBGA-272 |
| 文件页数： | 18/18页 |
| 文件大小： | 317K |
| 代理商： | ML69Q6203LA |
Oki Semiconductor 9
ML696201 and ML69Q6203
Preliminary
TDI
I
This pin is used during debugging. Normally set this input High
—
TDO
O
This pin is used during debugging. Normally, do not connect this pin to any trace
—
RTCK
O
This pin is used during debugging. Normally, do not connect this pin to any trace
—
External Bus Address and Data
XA [23:1]
O
Address of the bus that connects external RAM, external ROM, external IO and external DRAM
Secondary
XD [15:0]
I/O
Data bus that connects external RAM, external ROM, external IO and external DRAM
Secondary
External Bus Controls Signal
XOE_N
O
External memory access read enable, Active-Low
Secondary
XWE_N
O
External memory access write enable, Active-Low
Secondary
XROMCS_N
O
External ROM chip select, Active-Low
Secondary
XRAMCS_N
O
External RAM chip select, Active-Low
Secondary
XBS1_N
O
External memory byte select (MSB), Active-Low
Secondary
XBS0_N
O
External memory byte select (LSB), Active-Low
Secondary
XIOCS11_N
O
I/O bank 1, chip select 1, Active-Low
Secondary
XIOCS10_N
O
I/O bank 1, chip select 0, Active-Low
Secondary
XIOCS01_N
O
I/O bank 0, chip select 1, Active-Low
Secondary
XIOCS00_N
O
I/O bank 0, chip select 0, Active-Low
Secondary
XWAIT [1:0]
I
Wait signal for I/O bank 0/1.A device slower than the register set value can be connected by inputting this signal (wait
when 1).
Secondary
XSYSCLK
O
AHB clock for external bus
Secondary
External Bus Control Signals (DRAM)
XSDCS_N
O
SDRAM chip select, Active-Low
Secondary
XCAS_N
O
Column address strobe (SDRAM), Active-Low
Secondary
XRAS_N
O
Row address strobe (SDRAM), Active-Low
Secondary
XSDCLK
O
Clock for SDRAM
Secondary
XSDCKE
O
Clock enable (SDRAM)
Secondary
XDQM1
O
Input/output mask (MSB)
Secondary
XDQM0
O
Input/output mask (LSB)
Secondary
DMA Control
DREQ
I
DMA request signal. This signal is used if the DREQ type is set by the DMA controller.
Secondary
DREQCLR
O
DREQ signal clear request.
The DMA device turns off the DREQ signal when this signal is output.
Secondary
TCOUT
O
This signal noties the DAM device that the last transfer has been started.
Secondary
General-Purpose I/O Port
PIOA[15:0]
I/O
This is a general-purpose port. – Because this port has a secondary function, it cannot be used as a port if its secondary
function is used.
Primary
PIOB[15:0]
I/O
This is a general-purpose port. – Because this port has a secondary function, it cannot be used as a port if its secondary
function is used.
Primary
PIOC[15:0]
I/O
This is a general-purpose port.. – Because this port has a secondary function,it cannot be used as a port if its secondary
function is used.
Primary
PIOD [15:0]
I/O
This is a general-purpose port.. – Because this port has a secondary function,it cannot be used as a port if its secondary
function is used.
Primary
PIOE[15:0]
I/O
This is a general-purpose port.
PIOE[15] is 5-V tolerant.
PIOE[15:12] can be used as IRQ (interrupt requests)
Primary
PIOF[6:0]
I/O
This is a general-purpose port.. – Because this port has a secondary function,it cannot be used as a port if its secondary
function is used.
Primary
PLAT-SIO/UART
Pin Descriptions (Continued)
Symbol
I/O
Description
Primary/
Secondary
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