参数资料
型号: ML9040A-AXXWA
厂商: OKI ELECTRIC INDUSTRY CO LTD
元件分类: 显示控制器
英文描述: 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC81
封装: ALUMINUM PAD, DIE-81
文件页数: 13/49页
文件大小: 515K
代理商: ML9040A-AXXWA
ML9040A-Axx/-Bxx
Semiconductor
20/49
PEDL9040A-03
(2) When character pattern is 5 x 10 dots (see Table 3-2).
A method of writing character pattern into the CG RAM by the CPU:
Four bits of CG RAM address, bits 0-3, correspond to the line position of the character
pattern.
First, set increment or decrement with the CPU, and then input the address of the CG
RAM.
After this, write the character pattern code into the CG RAM, line by line from DB0-
DB7.
DB0 to DB7 correspond to CG RAM data, bits 0-7, in Table 3-2.
It is displayed when "H" is set as input data, while it is not displayed when "L" is set
as input data.
As the ADC is automatically incremented or decremented by 1 after the writing of
data to the CG RAM, it is not necessary to set the CG RAM address again.
The line, the CGRAM addresses 0-3 of which are "A" in hexadecimal notation, is the
cursor position. The CGRAM data is 0Red with the cursor at the cursor position and
displayed to LCD. For this reason, it is necessary to set all input data that become
cursor positions to "L".
When the CG RAM data, bits 0-4, and CG RAM addresses, bits 0-3, are "0" to "A", they
are displayed on the LCD as the display data. When the CG RAM data, bits of 5-7,
and CG RAM, bit data is 0-4 and CG RAM address data is "B" to "F", it is not output
to the LCD.
But in this case, CG RAM can be used as RAM and it can be written into/read out.
So, it can be used as the data RAM.
A method of displaying the CG RAM character pattern to the LCD:
The CG RAM is selected when 4-upper order bits of the character code are all "L".
As character code bits 0 and 3 are invalid, the display of "m" is selected by character
codes "00", "01", "08", and "09" (hex.) as in Table 3-2.
When the CG RAM character code is written to the DD RAM, the CG RAM character
pattern is displayed on the LCD display position corresponding to the DD RAM
address.
(DD RAM data bits 1 and 2 correspond to CG RAM address bits 4 and 5.)
相关PDF资料
PDF描述
ML9040A-BXXGA 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80
ML9040A-AXXWA 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC81
ML9040A-BXXWA 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC81
ML9041A-01ACVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189
ML9041A-01ACVWA 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC189
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