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参数资料
| 型号： | MM54HC646J |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 总线收发器 |
| 英文描述： | HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24 |
| 封装： | DIP-24 |
| 文件页数： | 3/6页 |
| 文件大小： | 188K |
| 代理商： | MM54HC646J |
Truth Table (Continued)
Inputs
Data IO
Operation or Function
G
DIR
CAB
CBA
SAB
SBA
A1 Thru A8
B1 Thru B8
’ALS646 ’ALS647
’ALS648 ’ALS649
’AS646
’AS648
LL
X
L
Output
Input
Real-Time B Data to A Bus
L
X
H
Stored B Data to A Bus
LH
X
L
X
Input
Output
Real-Time A Data to B Bus
L
H
X
H
X
Stored A Data to B Bus
H e High Level L e Low Level X e Irrelevant
u e low-to-high level transition
The data output functions ie data at the bus pins may be enabled or disabled by various signals at the G and DIR inputs Data input functions are always enabled
The data output functions ie data at the bus pins will be stored on every low-to-high transition on the clock inputs
AC Electrical Characteristics MM54HC646MM74HC646 MM54HC648MM74HC648
VCCe5V TAe25 C tretfe6ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
fMAX
Maximum Operating
MHz
Frequency
tPHL tPLH
Maximum Propagation
CLe
pF
ns
Delay A or B Input
to B or A Output
tPHL tPLH
Maximum Propagation
CLe
pF
ns
Delay CBA or CAB
Input to A or B Output
tPHL tPLH
Maximum Propagation
CLe
pF
ns
Delay SBA or SAB Input to A
or B Output with A or B high
tPHL tPLH
Maximum Propagation
CLe
pF
ns
Delay SBA or SAB Input to A
or B Output with A or B low
tPZH tPZL
Maximum Enable
RLe kX
ns
Time G or DIR Input to
CLe
pF
A or B Output
tPHZ tPLZ
Maximum Disable
RLe kX
ns
Time G or DIR Input to
CLe pF
A or B Output
AC Electrical Characteristics MM54HC646MM74HC646 MM54HC648MM74HC648
VCCe20–60V CLe50 pF tretfe6 ns (unless otherwise specified)
TAe25 C
74HC
54HC
Symbol
Parameter
Conditions
VCC
TAeb40 to 85 CTAeb55 to 125 C
Units
Typ
Guaranteed Limits
fMAX
Maximum Operating
CLe
pF
V
MHz
Frequency
V
MHz
V
MHz
tPHL tPLH
Maximum Propagation
CLe
pF
V
ns
Delay A or B Input
CLe
pF
V
ns
to B or A Output
CLe
pF
V
ns
CLe
pF
V
ns
CLe
pF
V
ns
CLe
pF
V
ns
tPHL tPLH
Maximum Propagation
CLe
pF
V
ns
Delay CBA or CAB
CLe
pF
V
ns
Input to A or B Output
CLe
pF
V
ns
CLe
pF
V
ns
CLe
pF
V
ns
CLe
pF
V
ns
3
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