参数资料
型号: MM74HC4040J
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 计数器
英文描述: HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, CDIP16
封装: DIP-16
文件页数: 3/8页
文件大小: 189K
代理商: MM74HC4040J
AC Electrical Characteristics
V
CC=5V, TA=25C, CL=15 pF, tr=tf=6ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Units
Limit
f
MAX
Maximum Operating
Frequency
50
30
MHz
t
PHL,tPLH
Maximum Propagation
(Note 6)
17
35
ns
Delay Clock to Q
t
PHL
Maximum Propagation
16
40
ns
Delay Reset to any Q
t
REM
Minimum Reset
10
20
ns
Removal Time
t
W
Minimum Pulse Width
10
16
ns
AC Electrical Characteristics
V
CC=2.0V to 6.0V, CL=50 pF, tr=tf=6 ns (unless otherwise specified)
T
A=25C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A=40 to 85C
T
A=55 to
125C
Units
Typ
Guaranteed Limits
f
MAX
Maximum Operating
2.0V
10
6
5
4
MHz
Frequency
4.5V
40
30
24
20
MHz
6.0V
50
35
28
24
MHz
t
PHL,tPLH
Maximum Propagation
2.0V
80
210
265
313
ns
Delay Clock to Q
1
4.5V
21
42
53
63
ns
6.0V
18
36
45
53
ns
T
PHL, tPLH
Maximum Propagation
2.0V
80
125
156
188
ns
Delay Between Stages
4.5V
18
25
31
38
ns
from Q
n to Qn+1
6.0V
15
21
26
31
ns
t
PHL
Maximum Propagation
2.0V
72
240
302
358
ns
Delay Reset to any Q
4.5V
24
48
60
72
ns
(’4020 and ’4040)
6.0V
20
41
51
61
ns
t
REM
Minimum Reset
2.0V
100
126
149
ns
Removal Time
4.5V
20
25
50
ns
6.0V
16
21
25
ns
t
W
Minimum Pulse Width
2.0V
90
100
120
ns
4.5V
16
20
24
ns
6.0V
14
18
20
ns
t
TLH,tTHL
Maximum
2.0V
30
75
95
110
ns
Output Rise
4.5V
10
15
19
22
ns
and Fall Time
6.0V
9
13
16
19
ns
t
r,tf
Maximum Input Rise and
1000
ns
Fall Time
500
ns
400
ns
C
PD
Power Dissipation
(per package)
55
pF
Capacitance (Note 7)
C
IN
Maximum Input
5
10
pF
Capacitance
Note 6: Typical Propagation delay time to any output can be calculated using: tP =17+12(N–1) ns; where N is the number of the output, QW,atVCC=5V.
Note 7: CPD determines the no load dynamic power consumption, PD=CPD VCC
2 f+I
CC VCC, and the no load dynamic current consumption, IS=CPD VCC f+ICC.
3
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