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参数资料
| 型号： | MM74HCT14SJX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 3/11页 |
| 文件大小： | 0K |
| 描述： | IC SCHMITT TRIGG HEX INV 14-SOP |
| 标准包装： | 2,000 |
| 系列： | 74HCT |
| 逻辑类型： | 逆变器，缓冲器 |
| 电路数： | 6 |
| 输入数： | 1 |
| 特点： | 施密特触发器 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 静态（最大值）： | 1µA |
| 输出电流高，低： | 4.8mA，4.8mA |
| 逻辑电平 - 低： | 0.5 V ~ 0.6 V |
| 逻辑电平 - 高： | 1.9 V ~ 2.1 V |
| 额定电压和最大 CL 时的最大传播延迟： | 20ns @ 5V，50pF |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 供应商设备封装： | 14-SOIC |
| 封装/外壳： | 14-SOIC（0.209"，5.30mm 宽） |
| 包装： | 带卷 (TR) |
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6143A Rev. 1.0.1
11
FMS6143A
—Three-Channel
6
th
-Order
Standard-Definition
VoltagePlus
Video
Filter
Driver
Layout Considerations
General layout and supply bypassing play a major role
in
high-frequency
performance
and
thermal
characteristics. Fairchild offers a demonstration board to
guide layout and aide device evaluation. The demo
board is a four-layer board with full power and ground
planes. Following this layout configuration provides
optimum performance and thermal characteristics for
the device. For the best results, follow the steps and
recommended routing rules listed below.
Recommended Routing/Layout Rules
Do not run analog and digital signals in parallel.
Use separate analog and digital power planes to
supply power.
Traces should run on top of the ground plane at all
times.
No trace should run over ground/power splits.
Avoid routing at 90-degree angles.
Minimize clock and video data trace length
differences.
Include 10μF and 0.1μF ceramic power supply
bypass capacitors.
Place the 0.1μF capacitor within 2.54mm (0.1in)
of the device power pin.
Place the 10μF capacitor within 19.05mm (0.75in)
of the device power pin.
For multi-layer boards, use a large ground plane to
help dissipate heat.
For two-layer boards, use a ground plane that
extends beyond the device body at least 12.7mm
(0.5in) on all sides. Include a metal paddle under
the device on the top layer.
Minimize all trace lengths to reduce series
inductance.
Output Considerations
The FMS6143A outputs are DC offset from the input by
150mV; therefore, VOUT = 2 x VIN DC + 150mV. This
offset is required to obtain optimal performance from the
output driver and is held at the minimum value to
decrease the standing DC current into the load. Since
the FMS6143A has a 2 x (6dB) gain, the output is
typically connected via a 75-series back-matching
resistor followed by the 75 video cable. Due to the
inherent divide-by-two of this configuration, the blanking
level at the load of the video signal is always less than
1V. When AC-coupling the output, ensure that the
coupling capacitor of choice passes the lowest
frequency content in the video signal and that line time
distortion (video tilt) is kept as low as possible.
The selection of the coupling capacitor is a function of
the subsequent circuit input impedance and the leakage
current of the input being driven. To obtain the highest
quality output video signal, the series termination
resistor must be placed as close to the device output pin
as possible. This greatly reduces the parasitic
capacitance and inductance effect on the output driver.
The distance from the device pin to the series termination
resistor should be no greater than 2.54mm (0.1in).
Figure 20.
Termination Resistor Placement
Thermal Considerations
Since the interior of most systems; such as set-top
boxes, TVs, and DVD players; are at TA=+70C;
consideration must be given to providing an adequate
heat sink for the device package for maximum heat
dissipation. When designing a system board, determine
how much power each device dissipates. Ensure that
devices of high power are not placed in the same
location, such as directly above (top plane) or below
(bottom plane) each other on the PCB.
PCB Thermal Layout Considerations
Understand the system power requirements and
environmental conditions.
Maximize thermal performance of the PCB.
Consider using 70μm of copper for high-power
designs.
Make the PCB as thin as possible by reducing FR4
thickness.
Use vias in the power pad to tie adjacent layers
together.
Remember that baseline temperature is a function
of board area, not copper thickness.
Modeling techniques provide a first-order
approximation.
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