参数资料
型号: MMA5224WR2
厂商: Freescale Semiconductor
文件页数: 14/58页
文件大小: 0K
描述: IC ACCELER 240G X-AXIS 16QFN
标准包装: 1,000
轴: X
加速范围: ±240g
灵敏度: 8LSB/g,4LSB/g,2LSB/g,1LSB/g
电源电压: 4.2 V ~ 17 V
输出类型: 数字
带宽: 400Hz
接口: SPI
安装类型: 表面贴装
封装/外壳: 16-QFN 裸露焊盘
供应商设备封装: 16-QFN(6x6)
3.1.3.3
Sync Pulse Pulldown Enable Bit (SYNC_PD)
The sync pulse pulldown enable bit selects if the sync pulse pulldown is enabled once a sync pulse is detected. Reference
Section 4.2.1.2 for more information regarding the sync pulse pulldown.
SYNC_PD
0
1
Sync Pulse Pulldown
Disabled
Enabled
If Daisy Chain Mode is enabled, the Sync Pulse Pulldown is enabled as listed below:
SYNC_PD
0
1
1
1
1
Daisy Chain Address
Programmed
x
No
Yes
Yes
Yes
“Run Mode”
Command Received
x
x
No
Yes
Yes
Daisy Chain Address = ‘001’
x
x
x
No
Yes
Sync Pulse Pulldown
Disabled
Enabled
Disabled
Disabled
Enabled
3.1.3.4
Latency Selection Bit (LATENCY)
The latency selection bit selects between one of two data latency methods to accommodate synchronized sampling or simul-
taneous sampling. Reference Section 4.5 for more information regarding latency and data synchronization.
Latency
0
1
Data Latency
Simultaneous Sampling Mode (Latency relative to Sync Pulse)
Synchronous Sampling Mode (Latency relative to Time Slot)
3.1.3.5
Data Size Selection Bit (DATASIZE)
The data size selection bit selects one of two data lengths for the PSI5 response message as shown below.
DATASIZE
0
1
Data Length
10 Bits
8 Bits
3.1.3.6
PSI5 Sync Pulse Blanking Time Selection Bit (BLANKTIME)
The PSI5 sync pulse blanking time selection bit selects the timing for ignoring sync pulses after successful reception of a sync
pulse. Reference Section 4.2.1.1 for details regarding sync pulse detection and blanking.
BLANKTIME
0
1
Blanking Time Method
Maximum of t SYNC_OFF_500 or Response Transmission Complete
Blanking Time determined by end of response transmission for programmed time slot
3.1.3.7
PSI5 Response Message Error Detection Selection Bit (P_CRC)
The PSI5 response message error detection selection bit selects either even parity, or a 3-Bit CRC for error detection of the
PSI5 response message. Reference Section 4.3.3 for details regarding response message error detection.
P_CRC
0
1
Parity or CRC
Parity
CRC
Note: The PSI5 specification recommends parity for data lengths of 10 bits or less.
MMA52xxKW
Sensors
14
Freescale Semiconductor, Inc.
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