参数资料
型号: MMA5224WR2
厂商: Freescale Semiconductor
文件页数: 50/58页
文件大小: 0K
描述: IC ACCELER 240G X-AXIS 16QFN
标准包装: 1,000
轴: X
加速范围: ±240g
灵敏度: 8LSB/g,4LSB/g,2LSB/g,1LSB/g
电源电压: 4.2 V ~ 17 V
输出类型: 数字
带宽: 400Hz
接口: SPI
安装类型: 表面贴装
封装/外壳: 16-QFN 裸露焊盘
供应商设备封装: 16-QFN(6x6)
5.3
5.3.1
Programming Mode Via PSI5 - Data Link Layer
Programming Mode Via PSI5 - Command Bit Encoding
Commands messages are transmitted via the modulation of the supply voltage. The presence of a sync pulse is a logic '1' and
the absence of a sync pulse is a logic '0'. Sync pulses are expected at a rate of t S-S_PM_L .
5.3.2
Programming Mode Via PSI5 - Command Message Format
Command message data frames consist of a start condition, 3 Start Bits (S[2:0]), a 3 bit Sensor Address (SAdr[2:0]), a 3-bit
Function Code (FC[2:0]), an optional Register Address (RAdr[5:0]), an optional data field (D[3:0]), and a 3-bit CRC (C[2:0]. The
start condition consists of one of the following:
1. A minimum of 5 consecutive logic ‘0’s (with not sync bits)
2. A minimum of 31 consecutive logic ‘1’s
The command message format is shown in Figure 41 .
Start Bits
Sensor Address
Function Code
Register Address
Data
CRC
Response
S2
S1
S0
SA0
SA1
SA2
FC0
FC1
FC2
RA0
RA1
RA2
RA3
RA4
RA5
D0
D1
D2
D3
C2
C1
C0
RC
RD1
RD0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
$3FF $3FF $3FF
CRC
Data to be written to register (optional)
Register Address (optional)
Function Codes for MMA52xx (Reference Section 5.3.6 )
Sensor Address - Fixed at 001 for MMA52xx
Start Bit Sequence = 010
Figure 40. Programming Mode Via PSI5 Command Data Format
Bit stuffing is necessary to maintain a synchronized time base between the command master and the device. A logic ‘1’ Sync
bit is added every 4 th bit in the command message to ensure there will never be more than 3 logic '0' bits in a row.
Start Bits
Sensor
Address
Function Code
Register Address
Data
CRC
Response
S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy RA0 RA1 RA2 Sy RA3 RA4 RA5 Sy D0 D1 D2 Sy D3 C2 C1 Sy C0
RC
RD1
RD0
0
1
0
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
1
0
$1E2
$3FF
$3FF
Figure 41. Programming Mode Via PSI5 Command Data Format with Sync Bits
Once a command is received and verified, the device expects 2 to 3 consecutive sync pulses (depending upon the command
message lengths described below). For each of these sync pulses, the device will respond with the following settings:
Parameter
Time Slot
Data Size
Error Checking
Baud Rate
Sync Pulse Pulldown
Register Bits
N/A
DATASIZE = 0
P_CRC = 0
BAUD
SYNCPD
Reference
N/A
Section 3.1.3.5
Section 3.1.3.7
Section 3.1.3.8
Section 3.1.3.3
Value
t TIMESLOT_DC1
10-bit data
Even Parity
125 kBaud
Disabled
Figure 42. Programming Mode Via PSI5 Response Message Settings
MMA52xxKW
Sensors
50
Freescale Semiconductor, Inc.
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