参数资料
型号: MMA5248W
厂商: Freescale Semiconductor
文件页数: 13/58页
文件大小: 0K
描述: IC ACCELER 480G X-AXIS 16QFN
标准包装: 75
轴: X
加速范围: ±480g
灵敏度: 8LSB/g,4LSB/g,2LSB/g,1LSB/g
电源电压: 4.2 V ~ 17 V
输出类型: 数字
带宽: 400Hz
接口: SPI
安装类型: 表面贴装
封装/外壳: 16-QFN 裸露焊盘
供应商设备封装: 16-QFN(6x6)
3.1.2
Factory Configuration Register (DEVCFG1)
The factory configuration register is a factory programmed, read only register which contains user specific device configuration
information. The factory configuration register is included in the factory programmed OTP CRC verification.
Location
Bit
Address
$04
Register
DEVCFG1
7
0
6
0
5
1
4
0
3
0
2
RNG[2]
1
RNG[1]
0
RNG[0]
Factory Default
0
0
1
0
0
0
0
0
3.1.2.1
Range Indication Bits (RNG[2:0])
The range indication bits are factory programmed and indicate the full-scale range of the device as shown below.
RNG[2]
0
0
0
0
1
1
1
1
RNG[1]
0
0
1
1
0
0
1
1
RNG[0]
0
1
0
1
0
1
0
1
Full-Scale Acceleration
Range
Reserved
±60g
Reserved
±120 g
Reserved
±240 g
Reserved
±480 g
g-Cell Design
N/A
Medium-g
N/A
Medium-g
N/A
High-g
N/A
High-g
PSI5 Init Data
Transmission (D9)
Reference Table 12
0001
0111
0010
1000
0011
1001
0100
1010
3.1.3
Device Configuration 2 Register (DEVCFG2)
Device configuration register 2 is a user programmable OTP register that contains device configuration information.
Location
Bit
Address
$05
Register
DEVCFG2
7
LOCK_U
6
PCM
5
SYNC_PD
4
LATENCY
3
DATASIZE
2
BLANKTIME
1
P_CRC
0
BAUD
Factory Default
0
0
0
0
0
0
0
0
3.1.3.1
User Configuration Lock Bit (LOCK_U)
The LOCK_U bit allows the user to prevent writes to the user configuration array once programming is completed.
If the LOCK_U bit is written to ‘1’ when a PSI5 “Execute Programming of NVM” command is executed, the LOCK_U OTP bit
will be programmed. Upon completion of the OTP programming, an OTP readout will be executed, locking the array from future
OTP writes. The User Programmable OTP Array Error Detection Verification is also activated (Reference Section 3.2.2 ).
3.1.3.2
PCM Enable Bit (PCM)
The PCM bit enables the PCM output pin. When the PCM bit is set, the PCM output pin is active and outputs a Pulse Code
Modulated signal proportional to the acceleration response. Reference Section 3.5.3.7 for more information regarding the PCM
output. When the PCM bit is cleared, the PCM output pin is actively pulled low.
PCM
0
1
PCM Output
Actively Pulled Low
PCM Signal Enabled
MMA52xxKW
Sensors
Freescale Semiconductor, Inc.
13
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