参数资料
型号: MMA5248W
厂商: Freescale Semiconductor
文件页数: 56/58页
文件大小: 0K
描述: IC ACCELER 480G X-AXIS 16QFN
标准包装: 75
轴: X
加速范围: ±480g
灵敏度: 8LSB/g,4LSB/g,2LSB/g,1LSB/g
电源电压: 4.2 V ~ 17 V
输出类型: 数字
带宽: 400Hz
接口: SPI
安装类型: 表面贴装
封装/外壳: 16-QFN 裸露焊盘
供应商设备封装: 16-QFN(6x6)
6.5.2
Register Read Command
The Register Read command format is shown in Table 20 . The least significant 8 bits of the Register Read command message
are ignored. The least significant 8 bits of the Register Read response message contain the contents of the register pointed to
by the register pointer.
16 bit register reads are possible using consecutive Register Read commands. The high byte of a 16 bit register will automat-
ically be frozen on a read of the low byte of the register.
6.5.3
Acceleration Data Read Operations
The Acceleration Data Read command format is shown in Table 20 . The response to this command provides either 8-bit, or
10-bit acceleration data depending on the state of the DATASIZE bit in the DEVCFG2 register.
DATASIZE
D15 D14 D13 D12 D11 D10 D9
Bit
D8 D7
D6
D5
D4
D3
D2
D1
D0
DATASIZE = 1 (8-Bit Data)
DATASIZE = 0 (10-Bit Data)
1
1
0
0
0
0
1
1
1
1
P
P
0
D9
0
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
6.5.4
6.5.4.1
Error Responses
Response to Invalid Commands
Reference Table 20 for responses to Invalid Commands.
6.5.4.2
Parity Fault Response
If the device detects a Command Parity fault, the current, and subsequent SPI commands are ignored and the device responds
to the subsequent message with the Parity Fault response, as shown in Table 20 .
6.6
SPI OTP Programming Procedure
1. Set V CC = V PP .
2. Enter SPI DPM.
3. Load desired data into the OTP shadow registers using SPI Write commands.
a. Write the desired contents of DEVCFG2 ($05) to address $05
b. Write the desired contents of DEVCFG2 ($05) to address $1E
c. Write the desired contents of DEVCFG3 ($06) to address $06
d. Write the desired contents of DEVCFG3 ($06) to address $1F
e. Write the desired contents of DEVCFG4 ($07) to address $07
f. Write the desired contents of DEVCFG4 ($07) to address $20
g. Write the desired contents of DEVCFG5 ($08) to address $08
h. Write the desired contents of DEVCFG5 ($08) to address $21
i. Write the desired contents of DEVCFG6 ($09) to address $09
j. Write the desired contents of DEVCFG6 ($09) to address $22
k. Write the desired contents of DEVCFG7 ($0A) to address $0A
l. Write the desired contents of DEVCFG7 ($0A) to address $23
m.Write the desired contents of DEVCFG8 ($0B) to address $0B
n. Write the desired contents of DEVCFG8 ($0B) to address $24
o. Write the desired contents of MFG_ID ($0D) to address $0D
p. Write the desired contents of MFG_ID ($0D) to address $2E
4. Write 0x05 to register $44 to initiate the NVM programming.
5. Delay a minimum of t PROG_ARRAY
6. Read the SC register and verify the IDEF_B flag is set (indicating the write is complete and successful).
MMA52xxKW
Sensors
56
Freescale Semiconductor, Inc.
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