参数资料
型号: MMA6823AKW
厂商: Freescale Semiconductor
文件页数: 14/54页
文件大小: 0K
描述: IC ACCELEROMETER XY AXIS 16QFN
标准包装: 75
轴: X,Y
加速范围: ±120g,±60g
灵敏度: 4.1 LSB/g,8.2 LSB/g
电源电压: 3.135 V ~ 5.25 V
输出类型: SPI
带宽: 400Hz
接口: SPI
安装类型: 表面贴装
封装/外壳: 16-QFN 裸露焊盘
供应商设备封装: 16-QFN-EP(6x6)
3.1.5
Device Control Register (DEVCTL)
The device control register is a read-write register which contains device control operations that can be applied during both
initialization and normal operation.
Table 7. Device Control Register
Location
Bit
Address
$0A
Register
DEVCTL
7
RES_1
6
RES_0
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Reset Value
0
0
0
0
0
0
0
0
3.1.5.1
Reset Control (RES_1, RES_0)
A series of three consecutive register write operations to the reset control bits in the DEVCTL register will cause a device reset.
To reset the internal digital circuitry, the following register write operations must be performed in the order shown below. The reg-
ister write operations must be consecutive SPI commands in the order shown or the device will not be reset.
Register Write to DEVCTL
SPI Register Write 1
SPI Register Write 2
SPI Register Write 3
RES_1
0
1
0
RES_0
0
1
1
Effect
No Effect
No Effect
Device RESET
The response to the Register Write returns ’0’ for RES_1 and RES_0. A Register Read of RES_1 and RES_0 returns ’0’ and
terminates the reset sequence.
3.1.5.2
Reserved Bits (DEVCTL[5:0])
Bits 5 through 0 of the DEVCTL register are reserved. A write to the reserved bits must always be logic ’0’ for normal device
operation and performance.
3.1.6
Device Configuration Register (DEVCFG)
The device configuration register is a read/write register which contains data for general device configuration. The register can
be written during initialization but is locked once the ENDINIT bit is set. This register is included in the writable register CRC
check. Refer to Section 3.2.2 for details.
Table 8. Device Configuration Register
Location
Bit
Address
$0B
Register
DEVCFG
7
Reserved
6
Reserved
5
ENDINIT
4
SD
3
OFMON
2
A_CFG[2]
1
A_CFG[1]
0
A_CFG[0]
Reset Value
0
0
0
0
0
0
0
0
3.1.6.1
Reserved Bits (Reserved)
Bits 6 and 7 of the DEVCFG register are reserved. A write to the reserved bits must always be logic ’0’ for normal device op-
eration and performance.
3.1.6.2
End of Initialization Bit (ENDINIT)
The ENDINIT bit is a control bit used to indicate that the user has completed all device and system level initialization tests,
and that MMA68xx will operate in normal mode. Once the ENDINIT bit is set, writes to all writable register bits are inhibited except
for the DEVCTL register. Once written, the ENDINIT bit can only be cleared by a device reset. The writable register CRC check
(reference Section 3.2.2 ) is only enabled when the ENDINIT bit is set.
MMA68xx
Sensors
14
Freescale Semiconductor, Inc.
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