参数资料
型号: MMA8453QR1
厂商: Freescale Semiconductor
文件页数: 19/47页
文件大小: 0K
描述: IC ACCELER 2G/4G/8G 3AXIS 16QFN
标准包装: 1
系列: MMA
轴: X,Y,Z
加速范围: ± 2g,4g,8g
灵敏度: 256LSB/g,128LSB/g,64LSB/g
电源电压: 1.95 V ~ 3.6 V
输出类型: 数字
带宽: 800Hz
接口: I²C
安装类型: 表面贴装
封装/外壳: 16-VFQFN
供应商设备封装: 16-QFN(3x3)
其它名称: MMA8453QR1DKR
Table 12. Register Address Map
PULSE_TMLT (1)(3)
R/W
0x26
0x27
00000000
0x00
Time limit for pulse
PULSE_LTCY
(1)(3)
R/W
0x27
0x28
00000000
0x00
Latency time for 2 nd pulse
PULSE_WIND (1)(3)
R/W
0x28
0x29
00000000
0x00
Window time for 2nd pulse
ASLP_COUNT
(1)(3)
R/W
0x29
0x2A
00000000
0x00
Counter setting for Auto-SLEEP
CTRL_REG1
(1)(3)
CTRL_REG2 (1)(3)
CTRL_REG3 (1)(3)
CTRL_REG4 (1)(3)
CTRL_REG5 (1)(3)
OFF_X (1)(3)
OFF_Y (1)(3)
OFF_Z (1)(3)
Reserved (do not modify)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x40 – 7F
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x0D
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ODR = 800 Hz, STANDBY Mode.
Sleep Enable, OS Modes,
RST, ST
Wake from Sleep, IPOL, PP_OD
Interrupt enable register
Interrupt pin (INT1/INT2) map
X-axis offset adjust
Y-axis offset adjust
Z-axis offset adjust
Reserved. Read return 0x00.
1. Register contents are preserved when transition from ACTIVE to STANDBY mode occurs.
2. Register contents are reset when transition from STANDBY to ACTIVE mode occurs.
3. Modification of this register’s contents can only occur when device is STANDBY mode except CTRL_REG1 ACTIVE bit and CTRL_REG2
RST bit.
Note : Auto-increment addresses which are not a simple increment are highlighted in bold . The auto-increment addressing is only enabled when
device registers are read using I 2 C burst read mode. Therefore the internal storage of the auto-increment address is cleared whenever a
stop-bit is detected.
6.1
Data Registers
The following are the data registers for the MMA8453Q. For more information on data manipulation of the MMA8453Q, refer
to application note, AN4076 .
0x00 STATUS: Data Status Register (Read Only)
Bit 7
ZYXOW
Bit 6
ZOW
Bit 5
YOW
Bit 4
XOW
Bit 3
ZYXDR
Bit 2
ZDR
Bit 1
YDR
Bit 0
XDR
Table 13. STATUS Description
X, Y, Z-axis Data Overwrite. Default value: 0
ZYXOW
ZOW
YOW
XOW
ZYXDR
ZDR
YDR
XDR
0: No data overwrite has occurred
1: Previous X, Y, or Z data was overwritten by new X, Y, or Z data before it was read
Z-axis Data Overwrite. Default value: 0
0: No data overwrite has occurred
1: Previous Z-axis data was overwritten by new Z-axis data before it was read
Y-axis Data Overwrite. Default value: 0
0: No data overwrite has occurred
1: Previous Y-axis data was overwritten by new Y-axis data before it was read
X-axis Data Overwrite. Default value: 0
0: No data overwrite has occurred
1: Previous X-axis data was overwritten by new X-axis data before it was read
X, Y, Z-axis new Data Ready. Default value: 0
0: No new set of data ready
1: A new set of data is ready
Z-axis new Data Available. Default value: 0
0: No new Z-axis data is ready
1: A new Z-axis data is ready
Y-axis new Data Available. Default value: 0
0: No new Y-axis data ready
1: A new Y-axis data is ready
X-axis new Data Available. Default value: 0
0: No new X-axis data ready
1: A new X-axis data is ready
MMA8453Q
Sensors
Freescale Semiconductor, Inc.
19
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