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| 型号： | MPC5534EVBISYS |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 53/60页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL ISYSTEMS MPC5534 |
| 标准包装： | 1 |
| 类型： | 微控制器 |
| 适用于相关产品： | MPC5534 |
| 所含物品： | 评估板和演示软件 |
| 相关产品： | MPC5554MZP132R2-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MZP132-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MVR132R2-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554MVR132-ND - IC MCU 2M FLASH 132MHZ 416-PBGA MPC5554AZP132-ND - IC MPU 2M FLASH 132MHZ 416-PBGA |
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Revision History for the MPC5534 Data Sheet
MPC5534 Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
57
Table 17, Pad AC Specifications, and Table 18, Derated Pad AC Specifications: The changes are identical in the tables.
Footnote 1, deleted ‘FSYS = 80 MHz’
Footnote 2, changed from ‘tested’ to ‘(not tested).’
Footnote 3, changed from ‘Out delay. . .’ to ‘The output delay. . .’,
Changed from ‘ Add a maximum of one system clock to the output delay to get the output delay with respect to
the system clock‘ to ‘To calculate the output delay with respect to the system clock, add a maximum of one system
clock to the output delay.’
Footnote 4: changed ‘Delay’ to ‘The output delay.’
Footnote 5: deleted ‘before qualification.’
Changed from ‘This parameter is supplied for reference and is not guaranteed by design and not tested’ to ‘This
parameter is supplied for reference and is guaranteed by design and tested.’
Table 20, JTAG Pin AC Electrical Characteristics:
Footnote 1, deleted: ‘, and CL = 30 pF with DSC = 0b10, SRC = 0b11’
Footnote 1, changed ‘functional’ to ‘Nexus.’
Table 21, Nexus Debug Port Timing.
Changed Spec 12, TCK Low to TDO Data Valid: Changed ‘VDDE = 3.0 to 3.6 volts’ maximum value in column 4
from 9 to 10. Now reads ‘VDDE = 3.0–3.6 V’ with a max value of 10.
Table 22, Bus Operation Timing:
External Bus Frequency: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is
the maximum speed allowed including frequency modulation (FM). 42 MHz parts allow for 40 MHz system clock
+ 2% FM; 68 MHz parts allow for 66 MHz system clock + 2% FM, and 82 MHz parts allow for
80 MHz system clock + 2% FM.
Spec 1: Changed the system frequency columns from 40, 56, and 66 MHz to 20, 33, and 40 MHz. Changed the
values in Min. columns: 20 MHz from 25 to 24.4; 33 MHz from 17.9 to 17.5, and 40 MHz from 15.2 to 14.9.
Specs 5 and 6: CLKOUT positive edge to output signals invalid of high: Corrected format to show the bus timing
values for various frequencies with EBTS bit = 0 and EBTS bit = 1.
Specs 5 and 6: Changed the following calibration signals: CAL_ADDR[8:30] to CAL_ADDR[10:30], and
CAL_WE/BE[0:1] to CAL_WE[0:1]. Deleted TEA.
Specs 7 and 8: Changed the following calibration signals: CAL_ADDR[8:30] to CAL_ADDR[10:30]. Deleted TEA.
BDIP, OE, RD_WR, and WE/BE[0:1]. CAL_CS[0, 2:3], CAL_OE, CAL_RD_WR, and CAL_WE/BE[0:1].
Table 23, External Interrupt Timing:
Footnote 1: Changed ‘VDDEH = 3.0–5.5;’ to ‘VDDEH = 3.0–5.25;’
Footnote 1: Deleted ‘FSYS = 80 MHz.’,‘VDD = 1.35–1.65 V’, ‘VDD33 and VDDSYN = 3.0–3.6 V.’ and
‘ and CL = 200 pF with SRC = 0b11.’
Deleted second figure after table ‘External Interrupt Setup Timing.’
Table 24, eTPU Timing
Footnote 1: Changed ‘VDDEH = 3.0–5.5;’ to ‘VDDEH = 3.0–5.25;’
Footnote 1: Deleted ‘FSYS = 80 MHz.’, ‘VDD = 1.35–1.65 V’, ‘VDD33 and VDDSYN = 3.0–3.6’ and
‘and CL = 200 pF with SRC = 0b11.’
Deleted second figure, ‘eTPU Input/Output Timing’ after this table.
Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Table 30. Table and Figure Changes Between Rev. 3.0 and 4.0 (continued)
Location
Description of Changes
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