参数资料
型号: MPC5553EVBE
厂商: Freescale Semiconductor
文件页数: 42/68页
文件大小: 0K
描述: BOARD EVAL FOR MPC5553
产品培训模块: MPC55xx PitchPak Family
标准包装: 1
类型: MCU
适用于相关产品: MPC5553
所含物品: 评估板和演示软件
配用: MFR4310FRDC-ND - FRDC FLEXRAY DAUGHTER CARD
相关产品: MPC5553MZQ132-ND - IC MCU MPC5553 REV A 324-PBGA
MPC5553MZP132-ND - IC MCU MPC5553 REV A 416-PBGA
Electrical Characteristics
MPC5553 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
47
3.14.2
MII FEC Transmit Signal Timing
FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, FEC_TX_CLK
The transmitter functions correctly up to the FEC_TX_CLK maximum frequency of 25 MHz plus one
percent. There is no minimum frequency requirement. In addition, the processor clock frequency must
exceed twice the FEC_TX_CLK frequency.
The transmit outputs (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER) can be programmed to transition
from either the rising- or falling-edge of TX_CLK, and the timing is the same in either case. These options
allow the use of non-compliant MII PHYs.
Refer to the Fast Ethernet Controller (FEC) chapter of the device reference manual for details of this option
and how to enable it.
Table 29 lists MII FEC transmit channel timings.
Figure 29 shows MII FEC transmit signal timings listed in Table 29.
Figure 29. MII FEC Transmit Signal Timing Diagram
Table 29. MII FEC Transmit Signal Timing
Spec
Characteristic
Min.
Max
Unit
5
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
5
ns
6
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
25
ns
7
FEC_TX_CLK pulse-width high
35%
65%
FEC_TX_CLK period
8
FEC_TX_CLK pulse-width low
35%
65%
FEC_TX_CLK period
6
FEC_TX_CLK (input)
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
5
7
8
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MPC5553EVBE 制造商:Freescale Semiconductor 功能描述:MPC55xxEVB: MPC55xx Evaluation
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