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参数资料
| 型号： | MPC5554MZP132R2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 132 MHz, MICROCONTROLLER, PBGA416 |
| 封装： | 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, TEBGA-416 |
| 文件页数： | 12/54页 |
| 文件大小： | 841K |
| 代理商： | MPC5554MZP132R2 |
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MPC5554 Microcontroller Data Sheet, Rev. 3.0
Overview
Freescale Semiconductor
2
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565.
The MPC5554 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB)
unified cache. The next level in the hierarchy contains the 64-KB on-chip internal SRAM and
two-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and
data. The external bus interface is designed to support most of the standard memories used with the
MPC5xx family.
The complex input/output timer functions of the MPC5554 are performed by two enhanced time processor
unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware
channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action hardware
channels, variable number of parameters per channel, angle clock hardware, and additional control and
arithmetic instructions. The eTPU is programmed using a high-level programming language.
The less complex timer functions of the MPC5554 are performed by the enhanced modular input/output
system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,
pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include
edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications
interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of
timer channels and general-purpose input/output (GPIOs) signals.
The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC). The 416 package
has 40-channels.
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also determined by the SIU. The internal multiplexer submodule (SIU_DISR) provides
multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal
multiplexing.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC551x
and
MPC5533
products
in
208
MAPBGA
packages;
MPC5534
and
MPC5553
products
in
208
and
496
MAPBGA
packages;
MPC5554,
MPC5565,
MPC5566
and
MPC5567
products
in
496
MAPBGA
packages
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