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| 型号： | MPC5554MZP132R2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 132 MHz, MICROCONTROLLER, PBGA416 |
| 封装： | 27 X 27 MM, 1 MM PITCH, PLASTIC, MS-034AAL-1, TEBGA-416 |
| 文件页数： | 47/54页 |
| 文件大小： | 841K |
| 代理商： | MPC5554MZP132R2 |
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Revision History for the MPC5554 Data Sheet
MPC5554 Microcontroller Data Sheet, Rev. 3.0
Freescale Semiconductor
51
Table 5 ESD Ratings:
Changed footnote 2 from:
‘Device failure is defined as: ‘If after exposure to ESD pulses, the device no longer meets the device specification
requirements. Complete DC parametric and functional testing will be performed per applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.’
to:
Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot
temperature.
Table 6 VCR/POR Electrical Specifications:
Added footnote 1 to specs 1, 2, and 3 that reads: The internal POR signals are VPOR15, VPOR33, and VPOR5.
On power up, assert RESET before the internal POR negates. RESET must remain asserted until the power
supplies are within the operating conditions as specified in Table 9 DC Electrical Specifications. On power down,
assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts.
Reformatted columns.
Table 9 DC Electrical Specifications:
Added footnote that reads: VDDE2 and VDDE3 are limited to 2.25–3.6 V only if SIU_ECCR[EBTS] = 0; VDDE2 and
VDDE3 have a range of 1.6–3.6 V if SIU_ECCR[EBTS] =1.
Added (TA = TL to TH) to the table title.
Footnote 1, Changed ‘Typical program and erase times assume nominal supply values and operation at 25 oC’
to ‘Typical program and erase times are calculated at 25 oC operating temperature using nominal supply values..’
Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’
Table 19 Reset and Configuration Pin Timing:
Footnote 1: Removed VDD = 1.35–1.65 V.
Table 20 JTAG Pin AC Electrical Characteristics
Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V.
Table 22 Bus Operation Timing:
External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum
frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow
for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and 132 MHz parts
allow for 128 MHz system clock + 2% FM.
Specifications 5, 6, 7, and 8: Reordered the EBI signals within each specification.
Specifications 7 and 8: Removed EBI signals BDIP, OE, TSIZ[0:1], WE/BE[0:3].
Footnote 1: Removed VDD = 1.35–1.65 V, and VDD33 and VDDSYN = 3.0–3.6 V.
Footnote 8: Changed EBTS to SIU_ECCR[EBTS].
Table 23 External Interrupt Timing (IRQ Signals)
Footnote 1: Removed VDD = 1.35–1.65 V; changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 24 eTPU Timing
Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 25 eMIOS Timing
Footnote 1: Changed VDDEH = 3.0–5.5 V to VDDEH = 3.0–5.25 V.
Table 28. Changes Between Rev. 2.0 and 3.0 (continued)
Location
Description of Changes
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC551x
and
MPC5533
products
in
208
MAPBGA
packages;
MPC5534
and
MPC5553
products
in
208
and
496
MAPBGA
packages;
MPC5554,
MPC5565,
MPC5566
and
MPC5567
products
in
496
MAPBGA
packages
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