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| 型号： | MPC5604SEMLQR |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-144 |
| 文件页数： | 83/104页 |
| 文件大小： | 1729K |
| 代理商： | MPC5604SEMLQR |
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MPC560xS Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Overview
Freescale Semiconductor
8
1.3.2
Block Summary
Table 2 summarizes the functions of all blocks present in the MPC560xS series microcontrollers. Please note that the presence
and number of blocks varies by device and package.
Table 2. MPC560xS Series Block Summary
Block
Function
16-channel 2nd-generation Direct Memory
Access (eDMA)
Second-generation platform module capable of performing complex
data transfers with minimal intervention from a host processor via “n”
programmable channels
AHB crossbar switch “lite” (XBAR-Lite)
Internal busmaster
Analog-to-digital converter (ADC)
16-channel, 10-bit analog to digital converter
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed
according to the boot mode of the device
Clock generation module (CGM)
Provides logic and control required for the generation of system and
peripheral clocks
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Display control unit (DCU)
Generates all signals required to drive a TFT LCD display, allowing
blending of data of up to 16 layers; can also display external digital
video/graphics in the background plane
Deserial serial peripheral interface (DSPI)
Provides a synchronous serial interface for communication with
external devices
QuadSPI (QSPI)
Provides a synchronous serial bus for communication with external
serial flash memory and is optionally configurable as a third DSPI
module
Enhanced modular input output system
(eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and
variables
FlexCAN (controller area network)
Supports the standard CAN communications protocol
FMPLL (frequency-modulated phase-locked
loop)
Two FMPLLs generate high-speed system clocks and support
programmable frequency modulation
Inter-integrated circuit (I2C) bus
A two wire bidirectional serial bus that provides a simple and efficient
method of data exchange between devices
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode
LCD driver module
Provides 40 × 4 (frontplane drivers × backplane drivers) or 6 × 38
driver configuration for driving LCD segments
LINFlex controller
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Memory protection unit (MPU)
Provides hardware access control for all memory references
generated in a device
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