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参数资料
| 型号： | MPC5607BF0ACMG6R |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PBGA208 |
| 封装： | 17 X 17 MM, 1 MM PITCH, MO-152AAF-1, ROHS COMPLIANT, MAPBGA-208 |
| 文件页数： | 63/110页 |
| 文件大小： | 907K |
| 代理商： | MPC5607BF0ACMG6R |
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MPC5607B Microcontroller Data Sheet, Rev. 6
Electrical characteristics
Freescale Semiconductor
56
4.8
Power management electrical characteristics
4.8.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage
ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved:
HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD
power pin.
BV: High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV
power pin. Voltage values should be aligned with VDD.
LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
— LV_CFLA: Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_DFLA: Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
— LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
Figure 9. Voltage regulator capacitance connection
The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable
low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.
Care should also be taken to limit the serial inductance of the board to less than 5 nH.
C
REG
1
(L
V_COR/L
V
_DF
L
A)
DEVICE
VSS_LV
VDD_BV
VDD_LV
C
DE
C
1
(B
alla
st
decoup
ling)
VSS_LV
VDD_LV
VDD
VSS_LV
VDD_LV
CREG2 (LV_COR/LV_CFLA)
CREG3
CDEC2
DEVICE
VDD_BV
I
VDD_LVn
VREF
VDD
Voltage Regulator
VSS
VSS_LVn
(supply/IO decoupling)
(LV_COR/LV_PLL)
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