参数资料
型号: MPC603PFE233LX
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 233 MHz, RISC PROCESSOR, CQFP240
封装: 32 X 32 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, CERAMIC, QFP-240
文件页数: 2/40页
文件大小: 431K
代理商: MPC603PFE233LX
10
PID7v-603e Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Figure 2 provides the input timing diagram for the PID7v-603e.
Figure 2. Input Timing Diagram
11b
SYSCLK to all other inputs invalid (input hold)
1.0
1.0
ns
3
11c
HRESET to mode select inputs invalid (input hold)
(for DRTRY, QACK, and TLBISYNC)
0—0—
ns
4, 6, 7
Notes:
1. Input specications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the
rising edge of the input SYSCLK. Input and output timings are measured at the pin.
2. Address/data/transfer attribute input signals are composed of the following—A[0–31], AP[0–3], TT[0–4],
TC[0–1], TBST, TSIZ[0-2], GBL, DH[0–31], DL[0–31], DP[0–7].
3. All other input signals are composed of the following—TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA,
DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must
be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter
in question.
6. These values are guaranteed by design, and are not tested.
7. This specication is for conguration mode only. Also note that HRESET must be held asserted for a minimum
of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Table 7. Input AC Timing Specifications1 (Continued)
Vdd = AVdd = 2.5
± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105° C
Num
Characteristic
160, 166, 180,
200 MHz
220, 225, 233,
240 MHz
Unit
Notes
Min
Max
Min
Max
VM
SYSCLK
ALL INPUTS
VM = Midpoint Voltage (1.4 V)
10a
10b
11a
11b
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