- 您现在的位置：买卖IC网 > PDF目录80394 > MPC740PRX400RE (FREESCALE SEMICONDUCTOR INC) 32-BIT, 400 MHz, RISC PROCESSOR, CBGA255 PDF资料下载
参数资料
| 型号： | MPC740PRX400RE |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件页数： | 3/24页 |
| 文件大小： | 543K |
| 代理商： | MPC740PRX400RE |
XPC750P RISC Microprocessor Hardware Specications
11
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.2.3 60x Bus Output AC Specications
Table 10. provides the 60x bus output AC timing specications for the XPC750P as dened in Figure 5..
Output timing specications for the L2 bus are provided in Section 1.4.2.6, L2 Bus Output AC
Table 10. 60x Bus Output AC Timing Specifications1
At recommended operating conditions (See Table 3.), CL = 50 pF
2
Num
Characteristic
300,333,366,400 MHz
Unit
Notes
Min
Max
12
SYSCLK to Output Driven (Output
Enable Time)
0.5
ns
13
SYSCLK to Output Valid (TS, ABB,
ARTRY, DBB)
5.0
ns
5
14
SYSCLK to all other Outputs Valid (all
except TS, ABB, ARTRY, DBB)
5.0
ns
5
15
SYSCLK to Output Invalid (Output Hold)
1.0
ns
3
16
SYSCLK to Output High Impedance (all
except ABB, ARTRY, DBB)
6.0
ns
8
17
SYSCLK to ABB, DBB High Impedance
after precharge
1.0
t
sysclk
4,6,8
18
SYSCLK to ARTRY High Impedance
before precharge
5.5
ns
8
19
SYSCLK to ARTRY Precharge Enable
0.2*t
sysclk
+1.0
ns
3,4,7
20
Maximum Delay to ARTRY Precharge
1
t
sysclk
4,7
21
SYSCLK to ARTRY High Impedance
After Precharge
2
t
sysclk
4,7,8
Notes:
1. All output specications are measured from the 1.4V of the rising edge of SYSCLK to TTL
level (0.8 V or 2.0 V) of the signal in question. Both input and output timing are measured at
the pin.
2. All maximum timing specications assume CL = 50 pF.
3. This minimum parameter assumes CL = 0 pF.
4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers
given in the table must be multiplied by the period of SYSCLK to compute the actual time
duration of the parameter in question.
5. Output signal transitions from GND to 2.0V or OVdd to 0.8V.
6. Nominal precharge width for ABB and DBB is 0.5 tsysclk.
7. Nominal precharge width for ARTRY is 1.0 tsysclk.
8. Guaranteed by design and characterization.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相关PDF资料 |
PDF描述 |
|---|---|
| MPC8555EVTALF | 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783 |
| MB88152APNF-G-110-JN-ERE1 | 16.6 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MPC8547PXATGB | 32-BIT, 1200 MHz, MICROPROCESSOR, PBGA783 |
| MPC8547VTAQGB | 32-BIT, 1000 MHz, MICROPROCESSOR, PBGA783 |
| MB89538ACPV4 | 8-BIT, MROM, MICROCONTROLLER, PQCC64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC7410 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications Addendum |
| MPC7410_1 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC7410_10 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications Addendum |
| MPC74-103J | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Metal Plate Cement Resistors |
| MPC74-103K | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Metal Plate Cement Resistors |
发布紧急采购，3分钟左右您将得到回复。