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参数资料
| 型号： | MPC8241LVR166B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, PBGA357 |
| 封装： | 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357 |
| 文件页数： | 20/60页 |
| 文件大小： | 730K |
| 代理商： | MPC8241LVR166B |
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MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
27
Electrical and Thermal Characteristics
Figure 16. I2C Timing Diagram I
Table 14. I2C Output AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
(FDR[5] == 0)
× (D
FDR/16)/2N + (FDR[5]
== 1)
× (D
FDR/16)/2M
—
CLKs
1–3
2
Clock low period
DFDR/2
—
CLKs
1–3
3
SCL/SDA rise time (from 0.5
to 2.4 V)
——
ms
4
Data hold time
8.0 + (16
× 2FDR[4:2]) × (5 –
4({FDR[5],FDR[1]} == b’10) –
3({FDR[5],FDR[1]} == b’11) –
2({FDR[5],FDR[1]} == b’00) –
1({FDR[5],FDR[1]} == b’01))
—
CLKs
1–3
5
SCL/SDA fall time (from 2.4 to 0.5 V)
—
< 5
ns
5
6
Clock high time
DFDR/2
—
CLKs
1–3
7
Data setup time (MPC8241 as a
master only)
(DFDR/2) – (output data hold time)
—
CLKs
1, 3
8
Start condition setup time (for
repeated start condition only)
DFDR + (output start condition hold time)
—
CLKs
1–3
9
Stop condition setup time
4.0
—
CLKs
1, 2
Notes:
1. Units for these specifications are in SDRAM_CLK units.
2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency
divider register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The
qualified SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualified SCL, SDA
signals are delayed by the SDRAM_CLK clock times DFFSR times two plus one SDRAM_CLK clock. The resulting
delay value is added to the value in the table (where this note is referenced). See Figure 17.
3. DFDR is the decimal divider number indexed by FDR[5:0] value. Refer to Table 10-5 in the MPC8245 Integrated
Processor User’s Manual. FDR[x] refers to the frequency divider register I2CFDR bit x. N is equal to a variable
number that would make the result of the divide (data hold time value) equal to a number less than 16. M is equal
to a variable number that would make the result of the divide (data hold time value) equal to a number less than 9.
4. Since SCL and SDA are open-drain type outputs, which the MPC8241 can only drive low, the time required for SCL
or SDA to reach a high level depends on external signal capacitance and pull-up resistor values.
5. Specified at a nominal 50 pF load.
SCL
SDA
VM
6
2
1
4
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