参数资料
型号: MPC8241LVR200D
厂商: Freescale Semiconductor
文件页数: 34/58页
文件大小: 0K
描述: IC MPU 32BIT 200MHZ PPC 357-PBGA
标准包装: 44
系列: MPC82xx
处理器类型: 32-位 MPC82xx PowerQUICC II
速度: 200MHz
电压: 1.8V
安装类型: 表面贴装
封装/外壳: 357-BBGA
供应商设备封装: 357-PBGA(25x25)
包装: 托盘
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
4
Freescale Semiconductor
Features
– Write buffering for PCI and processor accesses
– Normal parity, read-modify-write (RMW), or ECC
– Data-path buffering between memory interface and processor
– Low-voltage TTL logic (LVTTL) interfaces
– 272 Mbytes of base and extended ROM/Flash/PortX space
– Base ROM space for 8-bit data path or same size as the SDRAM data path (32- or 64-bit)
– Extended ROM space for 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data path
– PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
programmable address strobe timing, data ready input signal (DRDY), and 4 chip selects
— 32-bit PCI interface
– Operates up to 66 MHz
– PCI 2.2-compatible
– PCI 5.0-V tolerance
– Dual address cycle (DAC) for 64-bit PCI addressing (master only)
– PCI locked accesses to memory
– Accesses to PCI memory, I/O, and configuration spaces
– Selectable big- or little endian operation
– Store gathering of processor-to-PCI write and PCI-to-memory write accesses
– Memory prefetching of PCI read accesses
– Selectable hardware-enforced coherency
– PCI bus arbitration unit (five request/grant pairs)
– PCI agent mode capability
– Address translation with two inbound and outbound units (ATU)
– Internal configuration registers accessible from PCI
— Two-channel integrated DMA controller (writes to ROM/PortX not supported)
– Direct mode or chaining mode (automatic linking of DMA transfers)
– Scatter gathering—read or write discontinuous memory
– 64-byte transfer queue per channel
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– Local-to-PCI memory
– PCI memory-to-local memory
— Message unit
– Two doorbell registers
– Two inbound and two outbound messaging registers
–I2O message interface
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