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| 型号： | MPC8241LVR200D |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 56/58页 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 200MHZ PPC 357-PBGA |
| 标准包装： | 44 |
| 系列： | MPC82xx |
| 处理器类型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 200MHz |
| 电压： | 1.8V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 357-BBGA |
| 供应商设备封装： | 357-PBGA（25x25） |
| 包装： | 托盘 |
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MPC8241 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
7
Electrical and Thermal Characteristics
4.1.2
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8241.
Table 2. Recommended Operating Conditions 1
Characteristic
Symbol
Recommended
Value
Unit
Notes
Supply voltage
VDD
1.8
± 100 mV
V
2
I/O buffer supply for PCI and standard; supply voltages for
memory bus drivers
GVDD_OVDD
3.3
± 0.3
V
2
CPU PLL supply voltage
AVDD
1.8
± 100 mV
2
PLL supply voltage—peripheral logic
AVDD21.8 ± 100 mV
V
2
PCI reference
LVDD
5.0
± 5%
V
4, 5, 6
3.3
± 0.3
V
5, 6, 7
Input voltage
PCI inputs
Vin
0 to 3.6 or 5.75
V
4, 7
All other inputs
0 to 3.6
V
8
Die-junction temperature
Tj
0 to 105
C
Notes:
1. Freescale has tested these operating conditions and recommends them. Proper device operation outside of these conditions
is not guaranteed.
2. Caution: GVDD_OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time including during power-on reset.
Note that GVDD_OVDD pins are all shorted together: This limit may be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences. Connections should not be made to individual PWRRING pins.
3. Caution: VDD/AVDD/AVDD2 must not exceed GVDD_OVDD by more than 0.6 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4. PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 5.0 V DC power supply.
5. Caution: LVDD must not exceed VDD/AVDD/AVDD2 by more than 5.4 V at any time, including during power-on reset. This limit
may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
6. Caution: LVDD must not exceed GVDD_OVDD by more than 3.0 V at any time, including during power-on reset. This limit may
be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
7. PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 3.3 V DC power supply.
8. Caution: Input voltage (Vin) must not be greater than the supply voltage (VDD/AVDD/AVDD2) by more than 2.5 V at all times
including during power-on reset. Input voltage (Vin) must not be greater than GVDD_OVDD by more than 0.6 V at all times
including during power-on reset.
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