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参数资料
| 型号： | MPC8245LZU350X |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352 |
| 文件页数： | 19/60页 |
| 文件大小： | 620K |
| 代理商： | MPC8245LZU350X |
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26
MPC8245 Integrated Processor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Notes:
1
Units for these specications are in SDRAM_CLK units.
2
The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in
the Frequency Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to
qualied signals. The qualied SCL and SDA are delayed signals from what is seen in real time on the
I2C bus. The qualied SCL, SDA signals are delayed by the SDRAM_CLK clock times DFFSR times 2
plus 1 SDRAM_CLK clock. The resulting delay value is added to the value in the table (where this note is
referenced). See Figure 15.
3
Since SCL and SDA are open-drain type outputs, which the MPC8245 can only drive low, the time
required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resis-
tor values.
4
Specied at a nominal 50pF load.
5DFDR is the decimal divider number indexed by FDR[5–0] value. Refer to the I
2C Interface chapter’s
Serial Bit Clock Frequency Divider Selections table. FDR[x] refers to the Frequency Divider Register
I2CFDR bit x. N is equal to a variable number that would make the result of the divide (Data Hold Time
value) equal to a number less than 16. M is equal to a variable number that would make the result of the
divide (Data Hold Time value) equal to a number less than 9.
Table 13. I2C Output AC Timing Specifications
At recommended operating conditions (see Table 2) with LVdd = 3.3 V ± 0.3V
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
(FDR[5] == 0) x (DFDR/16) / 2N +
(FDR[5] == 1) x (DFDR/16) / 2M
—
CLKs
1,2,5
2
Clock low period
DFDR / 2
—
CLKs
1,2,5
3
SCL/SDA rise time
(from 0.5 V to 2.4 V)
—
ms
3
4
Data hold time
8.0 + (16 x 2FDR[4–2]) x (5 -
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’11) -
2({FDR[5],FDR[1]} == b’00) -
1({FDR[5],FDR[1]} == b’01))
—
CLKs
1,2,5
5
SCL/SDA fall time
(from 2.4 V to 0.5 V)
—< 5
ns
4
6
Clock high time
DFDR / 2
—
CLKs
1,2,5
7
Data setup time
(MPC8245 as a master only.)
(DFDR / 2) - (Output data hold time)
—
CLKs
1,5
8
Start condition setup time
(for repeated start condition only)
DFDR + (Output start condition hold
time)
—
CLKs
1,2,5
9
Stop condition setup time
4.0
—
CLKs
1,2
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