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参数资料
| 型号： | MPC8245LZU350X |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352 |
| 文件页数： | 7/60页 |
| 文件大小： | 620K |
| 代理商： | MPC8245LZU350X |
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MPC8245 Integrated Processor Hardware Specications
15
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
8
Pin to pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides
any intentional skew added to the clocking signals from the variable length DLL synchronization feedback
loop, i.e. the amount of variance between the internal sys-logic_clk and the SDRAM_SYNC_IN signal
after the DLL is locked. While pin to pin skew between SDRAM_CLKs can be measured, the relationship
between the internal sys-logic_clk and the external SDRAM_SYNC_IN can not be measured and is
guaranteed by design.
loop delay vs. frequency of operation.
.
Figure 4. PCI_SYNC_IN Input Clock Timing Diagram
The graphs that follow dene the areas of DLL locking for various modes. The grey areas represent where
the DLL will lock.
Note the following bit descriptions and denitions:.
1. For Standard DLL mode (non extended) : Clear bit 7 (DLL_EXTEND) at offset 0x72. (Default)
2. For Extended DLL mode: Set bit 7 (DLL_EXTEND) at offset 0x72.
3. Normal Tap Delay (Default): Clear bit 2 (DLL_MAX_DELAY) at offset 0x76.
4. Max Tap Delay: Set bit 2 (DLL_MAX_DELAY) at offset 0x76.
Note: The DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished
by increasing the time between each of the 128 tap points in the delay line. Although this increased time
makes it easier to guarantee that the reference clock will be within the DLL lock range, it also means there
may be slightly more jitter in the output clock of the DLL, should the phase comparator shift the clock
between adjacent tap points.
5a
5b
VM
VM = Midpoint Voltage (1.4V)
2
3
CVIL
CVIH
1
PCI_SYNC_IN
VM
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