参数资料
型号: MPC8266ACVRLHDX
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 250 MHz, RISC PROCESSOR, PBGA516
封装: PLASTIC, BGA-516
文件页数: 44/52页
文件大小: 884K
代理商: MPC8266ACVRLHDX
MPC8260A PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 1.1
Freescale Semiconductor
49
Document Revision History
0.3
11/2001
Table 1: note 3
Section 2.1: Removal of “Warning” recommending use of bootstrap diodes. They are not
needed.
Table 9: Change to sp12.
Table 10: Change to sp32.
Note 2 for Table 16 and Table 17
Addition of note at beginning of Section 3.2
Note 1 for Table 18 and Table 19
Table 20: Additions to B27, C28, D25, D27, E26, G29, H26–28, N25, P29, AF25, AA25, AB27
0.4
2/2002
Note 2 for Table 2 (changes in italics): “...greater than
or equal to 266 MHz, 200 MHz CPM...”
Table 19: Core and bus frequency values for the following ranges of MODCK_HMODCK:
0011_000 to 0011_100 and 1011_000 to 1011_1000
Table 20: Notes added to pins at AE11, AF25, U5, and V4.
0.5
3/2002
Table 20: Modified notes to pins AE11 and AF25.
Table 20: Addition of note to pins AA1 and AG4 (Therm0 and Therm1).
0.6
3/2002
Table 20: Modified notes to pins AE11 and AF25.
0.7
5/2002
Section 1, “Features”: minimum supported core frequency of 150 MHz
Section 1, “Features”: updated performance values (under “Dual-issue integer core”)
Table 2: Note 2 (changes in italics): “...
less than or equal to 233 MHz, 166 MHz CPM...”
Table 2: Addition of note 3.
0.8
1/2003
Table 2: Modification to supply voltage ranges reflected in notes 2, 3, and 4.
Table 4: Addition of
θJB and θJC.
Table 7, Figure 8: Addition of sp42a/sp43a.
Figure 3, Figure 4: Addition of note for FCC output.
Table 14, Table 17, and Table 19: Removal of PLL bypass mode from clock tables.
0.9
8/2003
Note: In revision 0.3, sp30 (Table 10) was changed. This change was not previously recorded
in this “Document Revision History” Table.
Removal of “HiP4 PowerQUICC II Documentation” table. These supplemental specifications
have been replaced by revision 1 of the
MPC8260 PowerQUICC II Family Reference
Manual.
Figure 1 and Section 1, “Features”: Addition of MPC8255 notes
Addition of Figure 2
Addition of VCCSYN to “Note: Core, PLL, and I/O Supply Voltages” following Table 2
Addition of note 1 to Table 3
Table 4: Changes to
θJA and θJB and θJC.
Addition of notes or modifications to Figure 6, Figure 7, and Figure 8
Table 9: Change of sp10.
Addition of Table 15.
Addition of note 2 to Table 20
Table 20: Addition of FCC2 Rx and Tx [3,4] to CPM pins PD7, PD18, PD19, and PD29. Also,
the addition of SPICLK to PC19. They are documented correctly in the parallel I/O ports
chapter in the
MPC8260 PowerQUICC II Family Reference Manual but had previously
been omitted from Table 20.
1.0
9/2005
Document template update
1.1
03/2006
Addition of Table 12.
Table 23. Document Revision History (continued)
Revision
Date
Substantive Changes
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