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参数资料
| 型号： | MPC8306VMACDCA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA369 |
| 封装： | 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369 |
| 文件页数： | 43/76页 |
| 文件大小： | 474K |
| 代理商： | MPC8306VMACDCA |
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MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
48
Freescale Semiconductor
JTAG
Figure 36 provides the AC test load for TDO and the boundary-scan outputs of the MPC8306.
Figure 36. AC Test Load for the JTAG Interface
Figure 37 provides the JTAG clock input timing diagram.
Figure 37. JTAG Clock Input Timing Diagram
Figure 38 provides the TRST timing diagram.
Figure 38. TRST Timing Diagram
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
—
ns
5
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
19
9
ns
5, 6
6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
load (see Figure 36).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K)
going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals
(D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design and characterization.
Table 51. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)1 (continued)
At recommended operating conditions (see Table 2).
Parameter
Symbol2
Min
Max
Unit
Notes
Output
Z0 = 50
OVDD/2
RL = 50
JTAG
tJTKHKL
tJTGR
External Clock
VM
tJTG
tJTGF
VM = Midpoint Voltage (OVDD/2)
TRST
VM = Midpoint Voltage (OVDD/2)
VM
tTRST
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8306VMADDC | 制造商:Freescale Semiconductor 功能描述:MPC8306VMADDC - Bulk |
| MPC8306VMADDCA | 功能描述:微处理器 - MPU E300 MP 266 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8306VMADDCA | 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 266 MHz 369-LFBGA |
| MPC8306VMAFDCA | 功能描述:微处理器 - MPU E300 MP 333 RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8308 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor |
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