参数资料
型号: MPC8314VRAFDA
厂商: Freescale Semiconductor
文件页数: 20/101页
文件大小: 0K
描述: MPU POWERQUICC II PRO 620-PBGA
标准包装: 36
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 620-BBGA 裸露焊盘
供应商设备封装: 620-PBGA(29x29)
包装: 托盘
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
25
Ethernet: Three-Speed Ethernet, MII Management
9.2.1.2
MII Receive AC Timing Specifications
This table provides the MII receive AC timing specifications.
This figure provides the AC test load for eTSEC.
Figure 10. eTSEC AC Test Load
This figure shows the MII receive AC timing diagram.
Figure 11. MII Receive AC Timing Diagram RMII AC Timing Specifications
Table 26. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V ± 300 mv
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—400
ns
RX_CLK clock period 100 Mbps
tMRX
—40—
ns
RX_CLK duty cycle
tMRXH/tMRX
35
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
ns
RX_CLK clock rise VIL(min) to VIH(max)
tMRXR
1.0
4.0
ns
RX_CLK clock fall time VIH(max) to VIL(min)
tMRXF
1.0
4.0
ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock
reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the
time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time.
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. The frequency of RX_CLK should not exceed the TX_CLK by more than 300 ppm
Output
Z0 = 50
LVDD/2
RL = 50
RX_CLK
RXD[3:0]
tMRDXKH
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
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