参数资料
型号: MPC8315E-RDBA
厂商: Freescale Semiconductor
文件页数: 53/106页
文件大小: 0K
描述: BOARD MPU 8315 POWERQUICC II
标准包装: 1
系列: PowerQUICC II™ PRO
类型: MPU
适用于相关产品: MPC8315E
所含物品:
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
50
Freescale Semiconductor
PCI
This table shows the PCI AC Timing Specifications at 33 MHz.
This figure provides the AC test load for PCI.
Figure 35. PCI AC Test Load
Input hold from clock
tPCIXKH
0
ns
2, 4
Note:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
Table 51. PCI AC Timing Specifications at 33 MHz
Parameter
Symbol 1
Min
Max
Unit
Note
Clock to output valid
tPCKHOV
—11
ns
2
Output hold from clock
tPCKHOX
2—
ns
2
Clock to output high impedance
tPCKHOZ
—14
ns
2, 3
Input setup to clock
tPCIVKH
4.0
ns
2, 4
Input hold from clock
tPCIXKH
0
ns
2, 4
Note:
1. Note that the symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
Table 50. PCI AC Timing Specifications at 66 MHz (continued)
Parameter
Symbol 1
Min
Max
Unit
Note
Output
Z0 = 50
NVDD/2
RL = 50
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