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参数资料
| 型号： | MPC8321EVRADDCA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA516 |
| 封装： | 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, PBGA-516 |
| 文件页数： | 78/82页 |
| 文件大小： | 1059K |
| 代理商： | MPC8321EVRADDCA |
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
8
Freescale Semiconductor
Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
2.1.4
Input Capacitance Specification
Table 4 describes the input capacitance for the CLKIN pin in the MPC8323E.
2.2
Power Sequencing
The device does not require the core supply voltage (VDD) and IO supply voltages (GVDD and OVDD) to
be applied in any particular order. Note that during power ramp-up, before the power supplies are stable
and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input
and output pins are actively driven and cause contention and excessive current. In order to avoid actively
driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O
voltage (GVDD and OVDD) and assert PORESET before the power supplies fully ramp up. In the case
where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before
the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are
stable, wait for a minimum of 32 clock cycles before negating PORESET.
Note that there is no specific power down sequence requirement for the device. I/O voltage supplies
(GVDD and OVDD) do not have any ordering requirements with respect to one another.
Table 3. Output Drive Capability
Driver Type
Output Impedance
(
Ω)
Supply
Voltage
Local bus interface utilities signals
42
OVDD = 3.3 V
PCI signals
25
DDR1 signal
18
GVDD = 2.5 V
DDR2 signal
18
GVDD = 1.8 V
DUART, system control, I2C, SPI, JTAG
42
OVDD = 3.3 V
GPIO signals
42
OVDD = 3.3 V
Table 4. Input Capacitance Specification
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input capacitance for all pins except CLKIN
CI
68
pF
—
Input capacitance for CLKIN
CICLKIN
10
—
pF
1
Note:
1. The external clock generator should be able to drive 10 pF.
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相关代理商/技术参数 |
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|---|---|
| MPC8321EVRAFDC | 功能描述:微处理器 - MPU 8321 NOPB PBGA W/ ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8321EVRAFDC | 制造商:Freescale Semiconductor 功能描述:Embedded Networking Processor |
| MPC8321EVRAFDCA | 制造商:Freescale Semiconductor 功能描述:POWERQUICC, 32 BIT POWER ARCHITECTURE SOC, 333MHZ E300, QE, - Trays 制造商:Freescale Semiconductor 功能描述:IC MPU PWRQUICC 333MHZ 516BGA 制造商:Freescale Semiconductor 功能描述:MPC8321 Series 32 Bit 333 MHz PowerQUICC II Integrated Communication Processor 制造商:Freescale Semiconductor 功能描述:PowerQUICC, 32 Bit Power Architecture SoC, 333MHz e300, QE, PCI, USB2.0, DDR1/2, |
| MPC8321EZQADDC | 功能描述:微处理器 - MPU 8321 PBGA W/ ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8321EZQAFDC | 功能描述:微处理器 - MPU 8321 PBGA W/ ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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