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| 型号： | MPC8323VRADDC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 41/82页 |
| 文件大小： | 0K |
| 描述： | IC MPU PWRQUICC II 516-PBGA |
| 产品培训模块： | MPC8323E PowerQUICC II Pro Processor |
| 标准包装： | 40 |
| 系列： | MPC83xx |
| 处理器类型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 266MHz |
| 电压： | 1V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 516-BBGA |
| 供应商设备封装： | 516-FPBGA（27x27） |
| 包装： | 托盘 |
| 配用： | MPC8323E-RDB-ND - BOARD REFERENCE DESIGN |
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
46
Freescale Semiconductor
HDLC, BISYNC, Transparent, and Synchronous UART
Figure 38 provides the AC test load.
Figure 38. AC Test Load
Figure 39 and Figure 40 represent the AC timing from Table 51. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Inputs—External clock input hold time
tHEIXKH
1—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs
internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
Table 52. Synchronous UART AC Timing Specifications1
Characteristic
Symbol2
Min
Max
Unit
Outputs—Internal clock delay
tUAIKHOV
05.5
ns
Outputs—External clock delay
tUAEKHOV
110
ns
Outputs—Internal clock high impedance
tUAIKHOX
05.5
ns
Outputs—External clock high impedance
tUAEKHOX
18
ns
Inputs—Internal clock input setup time
tUAIIVKH
6—
ns
Inputs—External clock input setup time
tUAEIVKH
4—
ns
Inputs—Internal clock input hold time
tUAIIXKH
0—
ns
Inputs—External clock input hold time
tUAEIXKH
1—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUAIKHOX symbolizes the outputs
internal timing (UAI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are
invalid (X).
Table 51. HDLC, BISYNC, and Transparent UART AC Timing Specifications1 (continued)
Characteristic
Symbol2
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8323VRADDCA | 制造商:Freescale Semiconductor 功能描述:POWERQUICC, 32 BIT POWER ARCHITECTURE SOC, 266MHZ E300, QE, - Trays 制造商:Freescale Semiconductor 功能描述:IC MPU PWRQUICC 266MHZ 516BGA |
| MPC8323VRAFDC | 功能描述:微处理器 - MPU 8323 NOPB PBGA W/O ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8323VRAFDCA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications |
| MPC8323ZQADDC | 功能描述:微处理器 - MPU 8323 PBGA W/O ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8323ZQADDCA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications |
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