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参数资料
型号： MPC8323VRADDC
厂商： Freescale Semiconductor
文件页数： 6/82页
文件大小： 0K
描述： IC MPU PWRQUICC II 516-PBGA
产品培训模块： MPC8323E PowerQUICC II Pro Processor
标准包装： 40
系列： MPC83xx
处理器类型： 32-位 MPC83xx PowerQUICC II Pro
速度： 266MHz
电压： 1V
安装类型： 表面贴装
封装/外壳： 516-BBGA
供应商设备封装： 516-FPBGA（27x27）
包装： 托盘
配用： MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
14
Freescale Semiconductor
DDR1 and DDR2 SDRAM
Table 14 provides the recommended operating conditions for the DDR1 SDRAM component(s) of the
MPC8323E when Dn_GVDD(typ) = 2.5 V.
Table 15 provides the DDR1 capacitance Dn_GVDD(typ) = 2.5 V.
Delta input/output capacitance: DQ, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. D
n
_GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA =25°C, VOUT = Dn_GVDD ÷ 2,
VOUT (peak-to-peak) = 0.2 V.
Table 14. DDR1 SDRAM DC Electrical Characteristics for D
n
_GVDD(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
D
n
_GVDD
2.375
2.625
V
1
I/O reference voltage
MVREF
nREF
0.49
× Dn_GVDD
0.51
× Dn_GVDD
V2
I/O termination voltage
VTT
MVREF
nREF – 0.04
MVREF
nREF + 0.04
V
3
Input high voltage
VIH
MVREF
nREF + 0.15
D
n
_GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF
nREF – 0.15
V
—
Output leakage current
IOZ
–9.9
μA4
Output high current (VOUT = 1.95 V)
IOH
–16.2
—
mA
—
Output low current (VOUT = 0.35 V)
IOL
16.2
—
mA
—
Notes:
1. D
n
_GVDD is expected to be within 50 mV of the DRAM Dn_GVDD at all times.
2. MVREF
nREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREF
nREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF
nREF. This rail should track variations in the DC level of MVREFnREF.
4. Output leakage is measured with all outputs disabled, 0 V
≤ VOUT ≤ Dn_GVDD.
Table 15. DDR1 SDRAM Capacitance for D
n
_GVDD(typ) = 2.5 V Interface
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ,DQS
CIO
68
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. D
n
_GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25° C, VOUT = Dn_GVDD ÷ 2,
VOUT (peak-to-peak) = 0.2 V.
Table 13. DDR2 SDRAM Capacitance for D
n
_GVDD(typ) = 1.8 V
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