参数资料
型号: MPC8343CVRADD
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA620
封装: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-620
文件页数: 77/84页
文件大小: 1428K
代理商: MPC8343CVRADD
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
79
Document Revision History
22 Document Revision History
Table 58 provides a revision history of this document.
Table 58. Document Revision History
Revision
Date
Substantive Change(s)
12
2/2009
In Section 21.1, “System Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.
In Section 21.2, “PLL Power Supply Filtering,” in the second paragraph, changed “provide five
independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and “the
four AVDD pins.”
In Table 31, corrected tLBKHOV parameter to tLBKLOV (output data is driven on falling edge of clock in
DLL bypass mode). Similarly, made the same correction to Figure 17, Figure 19, and Figure 20 for
output signals.
In Table 49, “Operating Frequencies for PBGA,” modified row to say “DDR and DDR2 memory bus
frequency (MCLK)2”
In Tables 51 and 52 ("CSB Frequency Options for Host Mode" and "CSB Frequency Options for Agent
Mode"), added “DDR2 memory may be used at 133 MHz provided that the memory components are
specified for operation at this frequency” to note 2.
In Section 9.2, “USB AC Electrical Specifications,” clarified that AC table is for ULPI only.
In Table 59, updated note 1 to say the following: “For temperature range = C, processor frequency is
limited to 400 with a platform frequency of 266.”
Added footnote 10 to Table 47.
In Table 47, updated note 11 to say the following: “SEC1_TXD[3] is required an external pull-up
resistor. For proper functionality of the device, this pin must be pulled up or actively driven high
during a hard reset. No external pull-down resistors are allowed to be attached to this net.”
Added footnote 6 to Table 7.
In Table 7, updated the note 6 to say the following: “The Spread spectrum clocking. Is allowed with 1%
input frequency down-spread at maximum 50KHz modulation rate regardless of input frequency.”
11
7/2007
In Table 3, “Output Drive Capability,” changed the values in the Output Impedance column and added
USB to the seventh row.
In Section 21.7, “Pull-Up Resistor Requirements,deleted last two paragraphs and after first
paragraph, added a new paragraph.
Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”
10
3/2007
In Section 23, “Ordering Information,” replaced first paragraph and added a note.
In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph.
9
2/2007
Page 1, updated first paragraph to reflect PowerQUICC II information. Updated note after second
paragraph.
In the features list in Section 1, “Overview,” corrected DDR data rate to show 266 MHz for PBGA parts
for all silicon revisions.
In Table 54, “Suggested PLL Configurations,” added the following row:
Ref No: 823, SPMF: 1000, Core PLL: 0100011, 400-MHz Device Input Clock Freq: 33, CSB
Freq: 266, and Core Freq: 400.
In Figure 38, “JTAG Interface Connection,” updated with new figure.
In Section 23, “Ordering Information,” replicated note from document introduction.
In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced third sentence of first
paragraph directing customer to product summary page for available frequency configuration parts.
Updated back page information.
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