参数资料
型号: MPC8343CZQAGDX
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
封装: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620
文件页数: 82/92页
文件大小: 987K
代理商: MPC8343CZQAGDX
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
83
System Design Information
20.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8343E can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8343E system, and the
MPC8343E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins
of the MPC8343E. These decoupling capacitors should receive their power from separate VDD, OVDD,
GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance.
Capacitors may be placed directly under the device using a standard escape pattern. Others may surround
the part.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS tantalum or Sanyo
OSCON).
20.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of
the MPC8343E.
20.5
Output Buffer DC Impedance
The MPC8343E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 35). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
相关PDF资料
PDF描述
MPC8343EVRAGD 32-BIT, 400 MHz, RISC PROCESSOR, PBGA620
MPC8343VRAGD 32-BIT, 400 MHz, RISC PROCESSOR, PBGA620
MPC8343EVRADD 32-BIT, 266 MHz, RISC PROCESSOR, PBGA620
MPC8343ECZQADD 32-BIT, 266 MHz, RISC PROCESSOR, PBGA620
MPC8343EZQADDA 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620
相关代理商/技术参数
参数描述
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