参数资料
型号: MPC8343EVRAGDB
厂商: Freescale Semiconductor
文件页数: 10/80页
文件大小: 0K
描述: IC MPU POWERQUICC II 620-PBGA
标准包装: 36
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
电压: 1.2V
安装类型: 表面贴装
封装/外壳: 620-BBGA 裸露焊盘
供应商设备封装: 620-PBGA(29x29)
包装: 托盘
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
18
Freescale Semiconductor
DDR and DDR2 SDRAM
Figure 5 illustrates the DDR input timing diagram showing the tDISKEW timing parameter.
Figure 5. DDR Input Timing Diagram
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20 shows the DDR and DDR2 output AC timing specifications.
266 MHz
–750
750
200 MHz
–750
750
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the equation: tDISKEW = ± (T/4 – abs (tCISKEW)); where T is the clock period and abs (tCISKEW) is the absolute
value of tCISKEW.
3. This specification applies only to the DDR interface.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
tMCK
7.5
10
ns
2
ADDR/CMD/MODT output setup with respect to MCK
tDDKHAS
ns
3
400 MHz
1.95
333 MHz
2.40
266 MHz
3.15
200 MHz
4.20
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications (continued)
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW
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