参数资料
型号: MPC8347VRADDA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620
封装: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-620
文件页数: 115/120页
文件大小: 1349K
代理商: MPC8347VRADDA
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2
94
Freescale Semiconductor
Clocking
19 Clocking
Figure 40 shows the internal distribution of the clocks.
Figure 40. MPC8347EA Clock Subsystem
The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
is configured in PCI host or PCI agent mode. When the MPC8347EA is configured as a PCI host device,
CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (
÷2) and the multiplexors for
PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8347EA to function. When the
MPC8347EA is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN
signal should be tied to GND.
Core PLL
System PLL
DDR
LBIU
LSYNC_IN
LSYNC_OUT
LCLK[0:2]
MCK[0:5]
core_clk
e300 core
csb_clk to rest
CLKIN
csb_clk
MPC8347EA
6
DDR
Memory
Local Bus
PCI_CLK_OUT[0:4]
PCI_SYNC_OUT
PCI_CLK/
Clock
Unit
of the device
ddr_clk
lbiu_clk
CFG_CLKIN_DIV
PCI Clock
PCI_SYNC_IN
Device
Memory
Device
/n
to local bus
memory
controller
to DDR
memory
controller
DLL
Clock
Div
/2
Divider
5
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