参数资料
型号: MPC8347ZUAGF
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA672
封装: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件页数: 98/102页
文件大小: 1094K
代理商: MPC8347ZUAGF
MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
95
Document Revision History
22 Document Revision History
Table 66 provides a revision history of this document.
Table 66. Document Revision History
Revision
Date
Substantive Change(s)
11
2/2009
In Section 21.1, “System Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.
In Section 21.2, “PLL Power Supply Filtering,” in the second paragraph, changed “provide five
independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and
“the four AVDD pins.”
In Table 35, removed row for rise time (tI2CR). Removed minimum value of tI2CF. Added note 5 stating
that the device does not follow the I2C-BUS Specifications version 2.1 regarding the tI2CF AC
parameter.
In Table 54, corrected the max csb_clk to 266 MHz.
In Table 60, added PLL configurations 903, 923, A03, A23, and 503 for 533 MHz
In Table 35, corrected tLBKHOV parametr to tLBKLOV (output data is driven on falling edge of clock in
DLL bypass mode). Similarly, made the same correction to Figure 21, Figure 23, and Figure 24 for
output signals.
In Table 9.2, clarified that AC table is for ULPI only.
Added footnote 4 to Table 67.
In Table 67, updated note 1 to say the following: “For temperature range = C, processor frequency
is up to 667(TBGA) with a platform frequency of 333 and limited to 400 (PBGA) with a platform
frequency of 266.”
Added footnote 10 and 11 to Table 51 and Table 52.
In Table 51, Table 52, updated note 11 to say the following: “SEC1_TXD[3] is required an external
pull-up resistor. For proper functionality of the device, this pin must be pulled up or actively driven
high during a hard reset. No external pull-down resistors are allowed to be attached to this net.”
Added footnote 6 to Table 7.
In Table 7, updated the note 6 to say the following: “The Spread spectrum clocking. Is allowed with
1% input frequency down-spread at maximum 50KHz modulation rate regardless of input
frequency.”
In 8.1.1, removed the note “The potential applied to the input of a GMII, MII, TBI, RGMII, or RTBI
receiver may exceed the potential of the receiver power supply (that is, a RGMII driver powered from
a 3.6 V supply driving VOH into a RGMII receiver powered from a 2.5-V supply). Tolerance for
dissimilar RGMII driver and receiver supply potentials is implicit in these specifications.”
10
4/2007
In Table 3, “Output Drive Capability,” changed the values in the Output Impedance column and
added USB to the seventh row.
In Table 54, “Operating Frequencies for TBGA,” added column for 400 MHz.
In Section 21.7, “Pull-Up Resistor Requirements,deleted last two paragraphs and after first
paragraph, added a new paragraph.
Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”
9
3/2007
In Table 54, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency (
csb_clk)’
row, changed the value in the 533 MHz column to 100–333.
In Table 60, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK
Options,’ added row A03 between Ref. No. 724 and 804. Under the subhead ‘66 MHz
CLKIN/PCI_CLK Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306, changed
the CORE PLL value to 0000110.
In Section 23, “Ordering Information,” replaced first paragraph and added a note.
In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced first paragraph.
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