参数资料
型号: MPC8349ZUALFA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 667 MHz, MICROPROCESSOR, PBGA672
封装: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件页数: 8/112页
文件大小: 1295K
代理商: MPC8349ZUALFA
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
105
System Design Information
Figure 41. Driver Impedance Measurement
Two measurements give the value of this resistance and the strength of the driver current source. First, the
output voltage is measured while driving logic 1 without an external differential termination resistor. The
measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured while driving logic 1
with an external precision differential termination resistor of value Rterm. The measured voltage is
V2 =(1/(1/R1 +1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm × (V1/V2 –1). The
drive current is then Isource =V1/Rsource.
Table 64 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal OVDD, 105°C.
21.6
Configuration Pin Multiplexing
The MPC8349EA power-on configuration options can be set through external pull-up or pull-down
resistors of 4.7 k
Ω on certain output pins (see the customer-visible configuration pins). These pins are used
as output only pins in normal operation.
However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched
when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal
function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with
Table 64. Impedance Characteristics
Impedance
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
PCI Signals
(not including PCI
output clocks)
PCI Output Clocks
(including
PCI_SYNC_OUT)
DDR DRAM
Symbol
Unit
RN
42 Target
25 Target
42 Target
20 Target
Z0
Ω
RP
42 Target
25 Target
42 Target
20 Target
Z0
Ω
Differential
NA
ZDIFF
Ω
Note: Nominal supply voltages. See Table 1, Tj = 105°C.
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
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